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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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24ec3ff329
Add the PL022 SSP/SPI block to the PL1176 DTS file, also define the separate SSPCLK clock derived from the 24MHz chrystal. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
339 lines
8.8 KiB
Plaintext
339 lines
8.8 KiB
Plaintext
/*
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* Copyright 2014 Linaro Ltd
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "skeleton.dtsi"
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/ {
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model = "ARM RealView PB1176";
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compatible = "arm,realview-pb1176";
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chosen { };
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aliases {
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serial0 = &pb1176_serial0;
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serial1 = &pb1176_serial1;
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serial2 = &pb1176_serial2;
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serial3 = &pb1176_serial3;
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};
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memory {
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/* 128 MiB memory @ 0x0 */
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reg = <0x00000000 0x08000000>;
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};
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xtal24mhz: xtal24mhz@24M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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timclk: timclk@1M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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sspclk: sspclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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uartclk: uartclk@24M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&xtal24mhz>;
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};
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/* FIXME: this actually hangs off the PLL clocks */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-pb1176-soc", "simple-bus";
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regmap = <&syscon>;
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ranges;
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syscon: syscon@10000000 {
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compatible = "arm,realview-pb1176-syscon", "syscon";
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reg = <0x10000000 0x1000>;
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led@08.0 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x01>;
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label = "versatile:0";
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linux,default-trigger = "heartbeat";
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default-state = "on";
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};
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led@08.1 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x02>;
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label = "versatile:1";
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linux,default-trigger = "mmc0";
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default-state = "off";
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};
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led@08.2 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x04>;
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label = "versatile:2";
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linux,default-trigger = "cpu0";
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default-state = "off";
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};
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led@08.3 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x08>;
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label = "versatile:3";
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default-state = "off";
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};
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led@08.4 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x10>;
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label = "versatile:4";
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default-state = "off";
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};
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led@08.5 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x20>;
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label = "versatile:5";
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default-state = "off";
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};
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led@08.6 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x40>;
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label = "versatile:6";
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default-state = "off";
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};
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led@08.7 {
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compatible = "register-bit-led";
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offset = <0x08>;
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mask = <0x80>;
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label = "versatile:7";
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default-state = "off";
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};
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};
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/* Primary DevChip GIC synthesized with the CPU */
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intc_dc1176: interrupt-controller@10120000 {
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compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x10121000 0x1000>,
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<0x10120000 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,l220-cache";
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reg = <0x10110000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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/*
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* Override default cache size, sets and
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* associativity as these may be erroneously set
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* up by boot loader(s).
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*/
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arm,override-auxreg;
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cache-size = <131072>; // 128kB
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cache-sets = <512>;
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cache-line-size = <32>;
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};
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pmu {
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compatible = "arm,arm1176-pmu";
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer01: timer@10104000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10104000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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timer23: timer@10105000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x10105000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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arm,sp804-has-irq = <1>;
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clocks = <&timclk>, <&timclk>, <&pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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pb1176_rtc: rtc@10108000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x10108000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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pb1176_gpio0: gpio@1010a000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x1010a000 0x1000>;
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gpio-controller;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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pb1176_ssp: ssp@1010b000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x1010b000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sspclk>, <&pclk>;
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clock-names = "SSPCLK", "apb_pclk";
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};
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pb1176_serial0: serial@1010c000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1010c000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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pb1176_serial1: serial@1010d000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1010d000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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pb1176_serial2: serial@1010e000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1010e000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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pb1176_serial3: serial@1010f000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1010f000 0x1000>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&pclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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};
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/* These peripherals are inside the FPGA rather than the DevChip */
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fpga {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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fpga_charlcd: charlcd@10008000 {
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compatible = "arm,versatile-lcd";
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reg = <0x10008000 0x1000>;
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interrupt-parent = <&intc_fpga1176>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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/* This GIC on the board is cascaded off the DevChip GIC */
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intc_fpga1176: interrupt-controller@10040000 {
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compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x10041000 0x1000>,
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<0x10040000 0x100>;
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interrupt-parent = <&intc_dc1176>;
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interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
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};
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fpga_gpio0: gpio@10014000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x10014000 0x1000>;
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gpio-controller;
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interrupt-parent = <&intc_fpga1176>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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fpga_gpio1: gpio@10015000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x10015000 0x1000>;
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gpio-controller;
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interrupt-parent = <&intc_fpga1176>;
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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fpga_rtc: rtc@10017000 {
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compatible = "arm,pl031", "arm,primecell";
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reg = <0x10017000 0x1000>;
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interrupt-parent = <&intc_fpga1176>;
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interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pclk>;
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clock-names = "apb_pclk";
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};
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};
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};
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