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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ea8af0d2f2
When working with RC QPs, the FW sets the ECN capable bits for all
the RoCE v2 packets. On the other hand, for UD QPs, the driver needs
to set the the ECN capable bits in the Address Handler since the HW
generates each packet according to the Address Handler and not
the QP context.
If ECN is not enabled in NIC or switch, these bits are ignored.
Fixes: 2811ba51b0 ("IB/mlx5: Add RoCE fields to Address Vector")
Reviewed-by: Mark Bloch <markb@mellanox.com>
Signed-off-by: Majd Dibbiny <majd@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
146 lines
4.3 KiB
C
146 lines
4.3 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "mlx5_ib.h"
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static struct ib_ah *create_ib_ah(struct mlx5_ib_dev *dev,
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struct mlx5_ib_ah *ah,
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struct rdma_ah_attr *ah_attr)
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{
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enum ib_gid_type gid_type;
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int err;
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if (rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) {
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const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
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memcpy(ah->av.rgid, &grh->dgid, 16);
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ah->av.grh_gid_fl = cpu_to_be32(grh->flow_label |
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(1 << 30) |
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grh->sgid_index << 20);
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ah->av.hop_limit = grh->hop_limit;
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ah->av.tclass = grh->traffic_class;
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}
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ah->av.stat_rate_sl = (rdma_ah_get_static_rate(ah_attr) << 4);
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if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) {
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err = mlx5_get_roce_gid_type(dev, ah_attr->port_num,
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ah_attr->grh.sgid_index,
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&gid_type);
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if (err)
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return ERR_PTR(err);
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memcpy(ah->av.rmac, ah_attr->roce.dmac,
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sizeof(ah_attr->roce.dmac));
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ah->av.udp_sport =
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mlx5_get_roce_udp_sport(dev,
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rdma_ah_get_port_num(ah_attr),
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rdma_ah_read_grh(ah_attr)->sgid_index);
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ah->av.stat_rate_sl |= (rdma_ah_get_sl(ah_attr) & 0x7) << 1;
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if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
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#define MLX5_ECN_ENABLED BIT(1)
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ah->av.tclass |= MLX5_ECN_ENABLED;
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} else {
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ah->av.rlid = cpu_to_be16(rdma_ah_get_dlid(ah_attr));
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ah->av.fl_mlid = rdma_ah_get_path_bits(ah_attr) & 0x7f;
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ah->av.stat_rate_sl |= (rdma_ah_get_sl(ah_attr) & 0xf);
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}
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return &ah->ibah;
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}
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struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
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struct ib_udata *udata)
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{
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struct mlx5_ib_ah *ah;
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struct mlx5_ib_dev *dev = to_mdev(pd->device);
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enum rdma_ah_attr_type ah_type = ah_attr->type;
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if ((ah_type == RDMA_AH_ATTR_TYPE_ROCE) &&
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!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
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return ERR_PTR(-EINVAL);
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if (ah_type == RDMA_AH_ATTR_TYPE_ROCE && udata) {
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int err;
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struct mlx5_ib_create_ah_resp resp = {};
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u32 min_resp_len = offsetof(typeof(resp), dmac) +
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sizeof(resp.dmac);
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if (udata->outlen < min_resp_len)
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return ERR_PTR(-EINVAL);
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resp.response_length = min_resp_len;
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memcpy(resp.dmac, ah_attr->roce.dmac, ETH_ALEN);
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err = ib_copy_to_udata(udata, &resp, resp.response_length);
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if (err)
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return ERR_PTR(err);
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}
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ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
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if (!ah)
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return ERR_PTR(-ENOMEM);
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return create_ib_ah(dev, ah, ah_attr); /* never fails */
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}
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int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr)
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{
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struct mlx5_ib_ah *ah = to_mah(ibah);
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u32 tmp;
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memset(ah_attr, 0, sizeof(*ah_attr));
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ah_attr->type = ibah->type;
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tmp = be32_to_cpu(ah->av.grh_gid_fl);
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if (tmp & (1 << 30)) {
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rdma_ah_set_grh(ah_attr, NULL,
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tmp & 0xfffff,
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(tmp >> 20) & 0xff,
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ah->av.hop_limit,
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ah->av.tclass);
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rdma_ah_set_dgid_raw(ah_attr, ah->av.rgid);
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}
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rdma_ah_set_dlid(ah_attr, be16_to_cpu(ah->av.rlid));
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rdma_ah_set_static_rate(ah_attr, ah->av.stat_rate_sl >> 4);
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rdma_ah_set_sl(ah_attr, ah->av.stat_rate_sl & 0xf);
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return 0;
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}
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int mlx5_ib_destroy_ah(struct ib_ah *ah)
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{
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kfree(to_mah(ah));
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return 0;
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}
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