mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
6048801070
Patch adds AVX2/x86-64 implementation of Blowfish cipher, requiring 32 parallel blocks for input (256 bytes). Table look-ups are performed using vpgatherdd instruction directly from vector registers and thus should be faster than earlier implementations. Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
450 lines
9.5 KiB
ArmAsm
450 lines
9.5 KiB
ArmAsm
/*
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* x86_64/AVX2 assembler optimized version of Blowfish
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*
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* Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/linkage.h>
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.file "blowfish-avx2-asm_64.S"
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.data
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.align 32
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.Lprefetch_mask:
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.long 0*64
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.long 1*64
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.long 2*64
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.long 3*64
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.long 4*64
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.long 5*64
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.long 6*64
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.long 7*64
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.Lbswap32_mask:
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.long 0x00010203
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.long 0x04050607
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.long 0x08090a0b
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.long 0x0c0d0e0f
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.Lbswap128_mask:
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.byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
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.Lbswap_iv_mask:
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.byte 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0
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.text
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/* structure of crypto context */
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#define p 0
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#define s0 ((16 + 2) * 4)
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#define s1 ((16 + 2 + (1 * 256)) * 4)
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#define s2 ((16 + 2 + (2 * 256)) * 4)
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#define s3 ((16 + 2 + (3 * 256)) * 4)
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/* register macros */
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#define CTX %rdi
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#define RIO %rdx
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#define RS0 %rax
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#define RS1 %r8
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#define RS2 %r9
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#define RS3 %r10
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#define RLOOP %r11
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#define RLOOPd %r11d
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#define RXr0 %ymm8
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#define RXr1 %ymm9
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#define RXr2 %ymm10
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#define RXr3 %ymm11
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#define RXl0 %ymm12
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#define RXl1 %ymm13
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#define RXl2 %ymm14
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#define RXl3 %ymm15
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/* temp regs */
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#define RT0 %ymm0
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#define RT0x %xmm0
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#define RT1 %ymm1
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#define RT1x %xmm1
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#define RIDX0 %ymm2
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#define RIDX1 %ymm3
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#define RIDX1x %xmm3
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#define RIDX2 %ymm4
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#define RIDX3 %ymm5
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/* vpgatherdd mask and '-1' */
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#define RNOT %ymm6
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/* byte mask, (-1 >> 24) */
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#define RBYTE %ymm7
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/***********************************************************************
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* 32-way AVX2 blowfish
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***********************************************************************/
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#define F(xl, xr) \
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vpsrld $24, xl, RIDX0; \
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vpsrld $16, xl, RIDX1; \
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vpsrld $8, xl, RIDX2; \
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vpand RBYTE, RIDX1, RIDX1; \
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vpand RBYTE, RIDX2, RIDX2; \
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vpand RBYTE, xl, RIDX3; \
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\
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vpgatherdd RNOT, (RS0, RIDX0, 4), RT0; \
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vpcmpeqd RNOT, RNOT, RNOT; \
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vpcmpeqd RIDX0, RIDX0, RIDX0; \
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\
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vpgatherdd RNOT, (RS1, RIDX1, 4), RT1; \
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vpcmpeqd RIDX1, RIDX1, RIDX1; \
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vpaddd RT0, RT1, RT0; \
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\
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vpgatherdd RIDX0, (RS2, RIDX2, 4), RT1; \
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vpxor RT0, RT1, RT0; \
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\
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vpgatherdd RIDX1, (RS3, RIDX3, 4), RT1; \
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vpcmpeqd RNOT, RNOT, RNOT; \
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vpaddd RT0, RT1, RT0; \
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\
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vpxor RT0, xr, xr;
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#define add_roundkey(xl, nmem) \
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vpbroadcastd nmem, RT0; \
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vpxor RT0, xl ## 0, xl ## 0; \
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vpxor RT0, xl ## 1, xl ## 1; \
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vpxor RT0, xl ## 2, xl ## 2; \
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vpxor RT0, xl ## 3, xl ## 3;
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#define round_enc() \
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add_roundkey(RXr, p(CTX,RLOOP,4)); \
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F(RXl0, RXr0); \
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F(RXl1, RXr1); \
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F(RXl2, RXr2); \
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F(RXl3, RXr3); \
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\
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add_roundkey(RXl, p+4(CTX,RLOOP,4)); \
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F(RXr0, RXl0); \
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F(RXr1, RXl1); \
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F(RXr2, RXl2); \
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F(RXr3, RXl3);
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#define round_dec() \
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add_roundkey(RXr, p+4*2(CTX,RLOOP,4)); \
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F(RXl0, RXr0); \
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F(RXl1, RXr1); \
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F(RXl2, RXr2); \
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F(RXl3, RXr3); \
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\
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add_roundkey(RXl, p+4(CTX,RLOOP,4)); \
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F(RXr0, RXl0); \
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F(RXr1, RXl1); \
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F(RXr2, RXl2); \
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F(RXr3, RXl3);
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#define init_round_constants() \
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vpcmpeqd RNOT, RNOT, RNOT; \
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leaq s0(CTX), RS0; \
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leaq s1(CTX), RS1; \
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leaq s2(CTX), RS2; \
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leaq s3(CTX), RS3; \
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vpsrld $24, RNOT, RBYTE;
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#define transpose_2x2(x0, x1, t0) \
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vpunpckldq x0, x1, t0; \
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vpunpckhdq x0, x1, x1; \
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\
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vpunpcklqdq t0, x1, x0; \
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vpunpckhqdq t0, x1, x1;
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#define read_block(xl, xr) \
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vbroadcasti128 .Lbswap32_mask, RT1; \
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\
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vpshufb RT1, xl ## 0, xl ## 0; \
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vpshufb RT1, xr ## 0, xr ## 0; \
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vpshufb RT1, xl ## 1, xl ## 1; \
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vpshufb RT1, xr ## 1, xr ## 1; \
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vpshufb RT1, xl ## 2, xl ## 2; \
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vpshufb RT1, xr ## 2, xr ## 2; \
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vpshufb RT1, xl ## 3, xl ## 3; \
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vpshufb RT1, xr ## 3, xr ## 3; \
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\
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transpose_2x2(xl ## 0, xr ## 0, RT0); \
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transpose_2x2(xl ## 1, xr ## 1, RT0); \
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transpose_2x2(xl ## 2, xr ## 2, RT0); \
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transpose_2x2(xl ## 3, xr ## 3, RT0);
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#define write_block(xl, xr) \
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vbroadcasti128 .Lbswap32_mask, RT1; \
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\
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transpose_2x2(xl ## 0, xr ## 0, RT0); \
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transpose_2x2(xl ## 1, xr ## 1, RT0); \
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transpose_2x2(xl ## 2, xr ## 2, RT0); \
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transpose_2x2(xl ## 3, xr ## 3, RT0); \
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\
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vpshufb RT1, xl ## 0, xl ## 0; \
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vpshufb RT1, xr ## 0, xr ## 0; \
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vpshufb RT1, xl ## 1, xl ## 1; \
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vpshufb RT1, xr ## 1, xr ## 1; \
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vpshufb RT1, xl ## 2, xl ## 2; \
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vpshufb RT1, xr ## 2, xr ## 2; \
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vpshufb RT1, xl ## 3, xl ## 3; \
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vpshufb RT1, xr ## 3, xr ## 3;
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.align 8
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__blowfish_enc_blk32:
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/* input:
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* %rdi: ctx, CTX
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* RXl0..4, RXr0..4: plaintext
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* output:
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* RXl0..4, RXr0..4: ciphertext (RXl <=> RXr swapped)
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*/
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init_round_constants();
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read_block(RXl, RXr);
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movl $1, RLOOPd;
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add_roundkey(RXl, p+4*(0)(CTX));
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.align 4
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.L__enc_loop:
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round_enc();
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leal 2(RLOOPd), RLOOPd;
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cmpl $17, RLOOPd;
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jne .L__enc_loop;
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add_roundkey(RXr, p+4*(17)(CTX));
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write_block(RXl, RXr);
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ret;
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ENDPROC(__blowfish_enc_blk32)
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.align 8
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__blowfish_dec_blk32:
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/* input:
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* %rdi: ctx, CTX
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* RXl0..4, RXr0..4: ciphertext
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* output:
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* RXl0..4, RXr0..4: plaintext (RXl <=> RXr swapped)
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*/
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init_round_constants();
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read_block(RXl, RXr);
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movl $14, RLOOPd;
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add_roundkey(RXl, p+4*(17)(CTX));
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.align 4
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.L__dec_loop:
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round_dec();
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addl $-2, RLOOPd;
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jns .L__dec_loop;
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add_roundkey(RXr, p+4*(0)(CTX));
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write_block(RXl, RXr);
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ret;
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ENDPROC(__blowfish_dec_blk32)
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ENTRY(blowfish_ecb_enc_32way)
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/* input:
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* %rdi: ctx, CTX
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* %rsi: dst
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* %rdx: src
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*/
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vzeroupper;
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vmovdqu 0*32(%rdx), RXl0;
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vmovdqu 1*32(%rdx), RXr0;
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vmovdqu 2*32(%rdx), RXl1;
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vmovdqu 3*32(%rdx), RXr1;
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vmovdqu 4*32(%rdx), RXl2;
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vmovdqu 5*32(%rdx), RXr2;
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vmovdqu 6*32(%rdx), RXl3;
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vmovdqu 7*32(%rdx), RXr3;
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call __blowfish_enc_blk32;
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vmovdqu RXr0, 0*32(%rsi);
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vmovdqu RXl0, 1*32(%rsi);
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vmovdqu RXr1, 2*32(%rsi);
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vmovdqu RXl1, 3*32(%rsi);
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vmovdqu RXr2, 4*32(%rsi);
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vmovdqu RXl2, 5*32(%rsi);
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vmovdqu RXr3, 6*32(%rsi);
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vmovdqu RXl3, 7*32(%rsi);
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vzeroupper;
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ret;
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ENDPROC(blowfish_ecb_enc_32way)
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ENTRY(blowfish_ecb_dec_32way)
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/* input:
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* %rdi: ctx, CTX
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* %rsi: dst
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* %rdx: src
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*/
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vzeroupper;
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vmovdqu 0*32(%rdx), RXl0;
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vmovdqu 1*32(%rdx), RXr0;
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vmovdqu 2*32(%rdx), RXl1;
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vmovdqu 3*32(%rdx), RXr1;
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vmovdqu 4*32(%rdx), RXl2;
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vmovdqu 5*32(%rdx), RXr2;
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vmovdqu 6*32(%rdx), RXl3;
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vmovdqu 7*32(%rdx), RXr3;
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call __blowfish_dec_blk32;
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vmovdqu RXr0, 0*32(%rsi);
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vmovdqu RXl0, 1*32(%rsi);
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vmovdqu RXr1, 2*32(%rsi);
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vmovdqu RXl1, 3*32(%rsi);
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vmovdqu RXr2, 4*32(%rsi);
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vmovdqu RXl2, 5*32(%rsi);
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vmovdqu RXr3, 6*32(%rsi);
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vmovdqu RXl3, 7*32(%rsi);
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vzeroupper;
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ret;
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ENDPROC(blowfish_ecb_dec_32way)
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ENTRY(blowfish_cbc_dec_32way)
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/* input:
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* %rdi: ctx, CTX
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* %rsi: dst
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* %rdx: src
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*/
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vzeroupper;
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vmovdqu 0*32(%rdx), RXl0;
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vmovdqu 1*32(%rdx), RXr0;
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vmovdqu 2*32(%rdx), RXl1;
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vmovdqu 3*32(%rdx), RXr1;
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vmovdqu 4*32(%rdx), RXl2;
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vmovdqu 5*32(%rdx), RXr2;
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vmovdqu 6*32(%rdx), RXl3;
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vmovdqu 7*32(%rdx), RXr3;
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call __blowfish_dec_blk32;
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/* xor with src */
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vmovq (%rdx), RT0x;
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vpshufd $0x4f, RT0x, RT0x;
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vinserti128 $1, 8(%rdx), RT0, RT0;
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vpxor RT0, RXr0, RXr0;
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vpxor 0*32+24(%rdx), RXl0, RXl0;
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vpxor 1*32+24(%rdx), RXr1, RXr1;
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vpxor 2*32+24(%rdx), RXl1, RXl1;
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vpxor 3*32+24(%rdx), RXr2, RXr2;
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vpxor 4*32+24(%rdx), RXl2, RXl2;
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vpxor 5*32+24(%rdx), RXr3, RXr3;
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vpxor 6*32+24(%rdx), RXl3, RXl3;
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vmovdqu RXr0, (0*32)(%rsi);
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vmovdqu RXl0, (1*32)(%rsi);
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vmovdqu RXr1, (2*32)(%rsi);
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vmovdqu RXl1, (3*32)(%rsi);
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vmovdqu RXr2, (4*32)(%rsi);
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vmovdqu RXl2, (5*32)(%rsi);
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vmovdqu RXr3, (6*32)(%rsi);
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vmovdqu RXl3, (7*32)(%rsi);
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vzeroupper;
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ret;
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ENDPROC(blowfish_cbc_dec_32way)
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ENTRY(blowfish_ctr_32way)
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/* input:
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* %rdi: ctx, CTX
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* %rsi: dst
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* %rdx: src
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* %rcx: iv (big endian, 64bit)
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*/
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vzeroupper;
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vpcmpeqd RT0, RT0, RT0;
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vpsrldq $8, RT0, RT0; /* a: -1, b: 0, c: -1, d: 0 */
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vpcmpeqd RT1x, RT1x, RT1x;
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vpaddq RT1x, RT1x, RT1x; /* a: -2, b: -2 */
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vpxor RIDX0, RIDX0, RIDX0;
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vinserti128 $1, RT1x, RIDX0, RIDX0; /* a: 0, b: 0, c: -2, d: -2 */
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vpaddq RIDX0, RT0, RT0; /* a: -1, b: 0, c: -3, d: -2 */
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vpcmpeqd RT1, RT1, RT1;
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vpaddq RT1, RT1, RT1; /* a: -2, b: -2, c: -2, d: -2 */
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vpaddq RT1, RT1, RIDX2; /* a: -4, b: -4, c: -4, d: -4 */
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vbroadcasti128 .Lbswap_iv_mask, RIDX0;
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vbroadcasti128 .Lbswap128_mask, RIDX1;
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/* load IV and byteswap */
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vmovq (%rcx), RT1x;
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vinserti128 $1, RT1x, RT1, RT1; /* a: BE, b: 0, c: BE, d: 0 */
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vpshufb RIDX0, RT1, RT1; /* a: LE, b: LE, c: LE, d: LE */
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/* construct IVs */
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vpsubq RT0, RT1, RT1; /* a: le1, b: le0, c: le3, d: le2 */
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vpshufb RIDX1, RT1, RXl0; /* a: be0, b: be1, c: be2, d: be3 */
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vpsubq RIDX2, RT1, RT1; /* le5, le4, le7, le6 */
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vpshufb RIDX1, RT1, RXr0; /* be4, be5, be6, be7 */
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vpsubq RIDX2, RT1, RT1;
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vpshufb RIDX1, RT1, RXl1;
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vpsubq RIDX2, RT1, RT1;
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vpshufb RIDX1, RT1, RXr1;
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vpsubq RIDX2, RT1, RT1;
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vpshufb RIDX1, RT1, RXl2;
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vpsubq RIDX2, RT1, RT1;
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vpshufb RIDX1, RT1, RXr2;
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vpsubq RIDX2, RT1, RT1;
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vpshufb RIDX1, RT1, RXl3;
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vpsubq RIDX2, RT1, RT1;
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vpshufb RIDX1, RT1, RXr3;
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/* store last IV */
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vpsubq RIDX2, RT1, RT1; /* a: le33, b: le32, ... */
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vpshufb RIDX1x, RT1x, RT1x; /* a: be32, ... */
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vmovq RT1x, (%rcx);
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call __blowfish_enc_blk32;
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/* dst = src ^ iv */
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vpxor 0*32(%rdx), RXr0, RXr0;
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vpxor 1*32(%rdx), RXl0, RXl0;
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vpxor 2*32(%rdx), RXr1, RXr1;
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vpxor 3*32(%rdx), RXl1, RXl1;
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vpxor 4*32(%rdx), RXr2, RXr2;
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vpxor 5*32(%rdx), RXl2, RXl2;
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vpxor 6*32(%rdx), RXr3, RXr3;
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vpxor 7*32(%rdx), RXl3, RXl3;
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vmovdqu RXr0, (0*32)(%rsi);
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vmovdqu RXl0, (1*32)(%rsi);
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vmovdqu RXr1, (2*32)(%rsi);
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|
vmovdqu RXl1, (3*32)(%rsi);
|
|
vmovdqu RXr2, (4*32)(%rsi);
|
|
vmovdqu RXl2, (5*32)(%rsi);
|
|
vmovdqu RXr3, (6*32)(%rsi);
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|
vmovdqu RXl3, (7*32)(%rsi);
|
|
|
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vzeroupper;
|
|
|
|
ret;
|
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ENDPROC(blowfish_ctr_32way)
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