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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4688708271
Add clock ids for the upctl and publ controllers used for ddr control. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
265 lines
6.0 KiB
C
265 lines
6.0 KiB
C
/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
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/* core clocks from */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define CORE_PERI 5
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#define CORE_L2C 6
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#define ARMCLK 7
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/* sclk gates (special clocks) */
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#define SCLK_UART0 64
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#define SCLK_UART1 65
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#define SCLK_UART2 66
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#define SCLK_UART3 67
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#define SCLK_MAC 68
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#define SCLK_SPI0 69
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#define SCLK_SPI1 70
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#define SCLK_SARADC 71
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#define SCLK_SDMMC 72
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#define SCLK_SDIO 73
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#define SCLK_EMMC 74
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#define SCLK_I2S0 75
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#define SCLK_I2S1 76
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#define SCLK_I2S2 77
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#define SCLK_SPDIF 78
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#define SCLK_CIF0 79
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#define SCLK_CIF1 80
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#define SCLK_OTGPHY0 81
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#define SCLK_OTGPHY1 82
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#define SCLK_HSADC 83
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#define SCLK_TIMER0 84
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#define SCLK_TIMER1 85
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#define SCLK_TIMER2 86
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#define SCLK_TIMER3 87
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#define SCLK_TIMER4 88
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#define SCLK_TIMER5 89
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#define SCLK_TIMER6 90
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#define SCLK_JTAG 91
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#define SCLK_SMC 92
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#define SCLK_TSADC 93
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#define DCLK_LCDC0 190
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#define DCLK_LCDC1 191
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/* aclk gates */
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#define ACLK_DMA1 192
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#define ACLK_DMA2 193
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#define ACLK_GPS 194
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#define ACLK_LCDC0 195
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#define ACLK_LCDC1 196
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#define ACLK_GPU 197
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#define ACLK_SMC 198
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#define ACLK_CIF 199
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#define ACLK_IPP 200
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#define ACLK_RGA 201
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#define ACLK_CIF0 202
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#define ACLK_CPU 203
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#define ACLK_PERI 204
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/* pclk gates */
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#define PCLK_GRF 320
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#define PCLK_PMU 321
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#define PCLK_TIMER0 322
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#define PCLK_TIMER1 323
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#define PCLK_TIMER2 324
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#define PCLK_TIMER3 325
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#define PCLK_PWM01 326
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#define PCLK_PWM23 327
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#define PCLK_SPI0 328
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#define PCLK_SPI1 329
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#define PCLK_SARADC 330
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#define PCLK_WDT 331
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#define PCLK_UART0 332
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#define PCLK_UART1 333
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#define PCLK_UART2 334
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#define PCLK_UART3 335
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#define PCLK_I2C0 336
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#define PCLK_I2C1 337
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#define PCLK_I2C2 338
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#define PCLK_I2C3 339
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#define PCLK_I2C4 340
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#define PCLK_GPIO0 341
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#define PCLK_GPIO1 342
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#define PCLK_GPIO2 343
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#define PCLK_GPIO3 344
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#define PCLK_GPIO4 345
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#define PCLK_GPIO6 346
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#define PCLK_EFUSE 347
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#define PCLK_TZPC 348
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#define PCLK_TSADC 349
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#define PCLK_CPU 350
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#define PCLK_PERI 351
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#define PCLK_DDRUPCTL 352
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#define PCLK_PUBL 353
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/* hclk gates */
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#define HCLK_SDMMC 448
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#define HCLK_SDIO 449
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#define HCLK_EMMC 450
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#define HCLK_OTG0 451
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#define HCLK_EMAC 452
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#define HCLK_SPDIF 453
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#define HCLK_I2S0 454
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#define HCLK_I2S1 455
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#define HCLK_I2S2 456
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#define HCLK_OTG1 457
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#define HCLK_HSIC 458
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#define HCLK_HSADC 459
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#define HCLK_PIDF 460
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#define HCLK_LCDC0 461
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#define HCLK_LCDC1 462
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#define HCLK_ROM 463
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#define HCLK_CIF0 464
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#define HCLK_IPP 465
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#define HCLK_RGA 466
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#define HCLK_NANDC0 467
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#define HCLK_CPU 468
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#define HCLK_PERI 469
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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/* soft-reset indices */
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#define SRST_MCORE 2
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#define SRST_CORE0 3
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#define SRST_CORE1 4
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#define SRST_MCORE_DBG 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE0_WDT 12
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#define SRST_CORE1_WDT 13
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#define SRST_STRC_SYS 14
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#define SRST_L2C 15
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#define SRST_CPU_AHB 17
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#define SRST_AHB2APB 19
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#define SRST_DMA1 20
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#define SRST_INTMEM 21
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#define SRST_ROM 22
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#define SRST_SPDIF 26
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#define SRST_TIMER0 27
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#define SRST_TIMER1 28
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#define SRST_EFUSE 30
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_GPIO3 35
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#define SRST_UART0 39
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#define SRST_UART1 40
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#define SRST_UART2 41
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#define SRST_UART3 42
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#define SRST_I2C0 43
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#define SRST_I2C1 44
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#define SRST_I2C2 45
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#define SRST_I2C3 46
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#define SRST_I2C4 47
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#define SRST_PWM0 48
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#define SRST_PWM1 49
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#define SRST_DAP_PO 50
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#define SRST_DAP 51
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#define SRST_DAP_SYS 52
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#define SRST_TPIU_ATB 53
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#define SRST_PMU_APB 54
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#define SRST_GRF 55
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#define SRST_PMU 56
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#define SRST_PERI_AXI 57
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#define SRST_PERI_AHB 58
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#define SRST_PERI_APB 59
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#define SRST_PERI_NIU 60
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#define SRST_CPU_PERI 61
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#define SRST_EMEM_PERI 62
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#define SRST_USB_PERI 63
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#define SRST_DMA2 64
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#define SRST_SMC 65
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#define SRST_MAC 66
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#define SRST_NANC0 68
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#define SRST_USBOTG0 69
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#define SRST_USBPHY0 70
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#define SRST_OTGC0 71
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#define SRST_USBOTG1 72
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#define SRST_USBPHY1 73
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#define SRST_OTGC1 74
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#define SRST_HSADC 76
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#define SRST_PIDFILTER 77
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#define SRST_DDR_MSCH 79
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#define SRST_TZPC 80
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#define SRST_SDMMC 81
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#define SRST_SDIO 82
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#define SRST_EMMC 83
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#define SRST_SPI0 84
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#define SRST_SPI1 85
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#define SRST_WDT 86
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#define SRST_SARADC 87
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#define SRST_DDRPHY 88
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#define SRST_DDRPHY_APB 89
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#define SRST_DDRCTL 90
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#define SRST_DDRCTL_APB 91
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#define SRST_DDRPUB 93
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#define SRST_VIO0_AXI 98
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#define SRST_VIO0_AHB 99
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#define SRST_LCDC0_AXI 100
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#define SRST_LCDC0_AHB 101
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#define SRST_LCDC0_DCLK 102
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#define SRST_LCDC1_AXI 103
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#define SRST_LCDC1_AHB 104
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#define SRST_LCDC1_DCLK 105
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#define SRST_IPP_AXI 106
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#define SRST_IPP_AHB 107
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#define SRST_RGA_AXI 108
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#define SRST_RGA_AHB 109
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#define SRST_CIF0 110
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#define SRST_VCODEC_AXI 112
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#define SRST_VCODEC_AHB 113
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#define SRST_VIO1_AXI 114
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#define SRST_VCODEC_CPU 115
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#define SRST_VCODEC_NIU 116
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#define SRST_GPU 120
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#define SRST_GPU_NIU 122
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#define SRST_TFUN_ATB 125
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#define SRST_TFUN_APB 126
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#define SRST_CTI4_APB 127
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#define SRST_TPIU_APB 128
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#define SRST_TRACE 129
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#define SRST_CORE_DBG 130
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#define SRST_DBG_APB 131
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#define SRST_CTI0 132
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#define SRST_CTI0_APB 133
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#define SRST_CTI1 134
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#define SRST_CTI1_APB 135
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#define SRST_PTM_CORE0 136
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#define SRST_PTM_CORE1 137
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#define SRST_PTM0 138
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#define SRST_PTM0_ATB 139
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#define SRST_PTM1 140
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#define SRST_PTM1_ATB 141
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#define SRST_CTM 142
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#define SRST_TS 143
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#endif
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