Alban Bedel 24b0e3e84f MIPS: ath79: Improve the DDR controller interface ... The DDR controller need to be used by the IRQ controller to flush the write buffer of some devices before running the IRQ handler. It is also used by the PCI controller to setup the PCI memory windows. The current interface used to access the DDR controller doesn't provides any useful abstraction and simply rely on a shared global pointer. Replace this by a simple API to setup the PCI memory windows and use the write buffer flush independently of the SoC type. That remove the need for the shared global pointer, simplify the IRQ handler code. [ralf@linux-mips.org: Folded in Alban Bedel's follup fix.] Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Gabor Juhos <juhosg@openwrt.org> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9773/ Patchwork: http://patchwork.linux-mips.org/patch/10543/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-06-21 21:53:51 +02:00
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ar71xx_regs.h	MIPS: ath79: Correctly name the defines for the PLL_FB register	2015-06-21 21:53:49 +02:00
ar933x_uart.h	MIPS: Whitespace cleanup.	2013-02-01 10:00:22 +01:00
ath79_spi_platform.h	SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs	2011-01-18 19:30:27 +01:00
ath79.h	MIPS: ath79: Improve the DDR controller interface	2015-06-21 21:53:51 +02:00
cpu-feature-overrides.h	MIPS: ath79: Don't hardwire cpu_has_dsp{2} to 0	2013-09-03 23:22:16 +02:00
gpio.h	MIPS: ath79: add GPIOLIB support	2011-01-18 19:30:25 +01:00
irq.h	MIPS: ath79: add IRQ handling code for the QCA955X SoCs	2013-02-19 09:36:25 +01:00
kernel-entry-init.h	MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs	2011-01-18 19:30:24 +01:00