mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
0caafbde07
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data transfer rates. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
443 lines
12 KiB
Plaintext
443 lines
12 KiB
Plaintext
#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/gpio/tegra186-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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/ {
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compatible = "nvidia,tegra186";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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gpio: gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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reg = <0x0 0x2200000 0x0 0x10000>,
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<0x0 0x2210000 0x0 0x10000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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#gpio-cells = <2>;
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gpio-controller;
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};
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ethernet@2490000 {
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compatible = "nvidia,tegra186-eqos",
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"snps,dwc-qos-ethernet-4.10";
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reg = <0x0 0x02490000 0x0 0x10000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
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clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
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<&bpmp TEGRA186_CLK_EQOS_AXI>,
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<&bpmp TEGRA186_CLK_EQOS_RX>,
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<&bpmp TEGRA186_CLK_EQOS_TX>,
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<&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
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clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
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resets = <&bpmp TEGRA186_RESET_EQOS>;
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reset-names = "eqos";
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status = "disabled";
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snps,write-requests = <1>;
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snps,read-requests = <3>;
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snps,burst-map = <0x7>;
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snps,txpbl = <32>;
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snps,rxpbl = <8>;
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03100000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_UARTA>;
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clock-names = "serial";
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resets = <&bpmp TEGRA186_RESET_UARTA>;
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reset-names = "serial";
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status = "disabled";
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};
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uartb: serial@3110000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03110000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_UARTB>;
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clock-names = "serial";
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resets = <&bpmp TEGRA186_RESET_UARTB>;
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reset-names = "serial";
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status = "disabled";
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};
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uartd: serial@3130000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03130000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_UARTD>;
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clock-names = "serial";
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resets = <&bpmp TEGRA186_RESET_UARTD>;
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reset-names = "serial";
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status = "disabled";
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};
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uarte: serial@3140000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03140000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_UARTE>;
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clock-names = "serial";
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resets = <&bpmp TEGRA186_RESET_UARTE>;
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reset-names = "serial";
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status = "disabled";
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};
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uartf: serial@3150000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x03150000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_UARTF>;
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clock-names = "serial";
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resets = <&bpmp TEGRA186_RESET_UARTF>;
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reset-names = "serial";
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status = "disabled";
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};
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gen1_i2c: i2c@3160000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x03160000 0x0 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C1>;
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reset-names = "i2c";
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status = "disabled";
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};
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cam_i2c: i2c@3180000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x03180000 0x0 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C3>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux1 */
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dp_aux_ch1_i2c: i2c@3190000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x03190000 0x0 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C4>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* controlled by BPMP, should not be enabled */
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pwr_i2c: i2c@31a0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031a0000 0x0 0x10000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C5>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C5>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux0 */
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dp_aux_ch0_i2c: i2c@31b0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C6>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C6>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen7_i2c: i2c@31c0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031c0000 0x0 0x10000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C7>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C7>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen9_i2c: i2c@31e0000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x031e0000 0x0 0x10000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C9>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C9>;
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reset-names = "i2c";
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status = "disabled";
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};
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sdmmc1: sdhci@3400000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03400000 0x0 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA186_RESET_SDMMC1>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc2: sdhci@3420000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03420000 0x0 0x10000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA186_RESET_SDMMC2>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc3: sdhci@3440000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03440000 0x0 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA186_RESET_SDMMC3>;
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reset-names = "sdhci";
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status = "disabled";
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};
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sdmmc4: sdhci@3460000 {
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compatible = "nvidia,tegra186-sdhci";
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reg = <0x0 0x03460000 0x0 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA186_RESET_SDMMC4>;
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reset-names = "sdhci";
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status = "disabled";
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};
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gic: interrupt-controller@3881000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x03881000 0x0 0x1000>,
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<0x0 0x03882000 0x0 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra186-hsp";
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reg = <0x0 0x03c00000 0x0 0xa0000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "doorbell";
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#mbox-cells = <2>;
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status = "disabled";
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};
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gen2_i2c: i2c@c240000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x0c240000 0x0 0x10000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C2>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C2>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen8_i2c: i2c@c250000 {
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compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
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reg = <0x0 0x0c250000 0x0 0x10000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA186_CLK_I2C8>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA186_RESET_I2C8>;
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reset-names = "i2c";
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status = "disabled";
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};
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uartc: serial@c280000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x0c280000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_UARTC>;
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clock-names = "serial";
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resets = <&bpmp TEGRA186_RESET_UARTC>;
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reset-names = "serial";
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status = "disabled";
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};
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uartg: serial@c290000 {
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compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
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reg = <0x0 0x0c290000 0x0 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_UARTG>;
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clock-names = "serial";
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resets = <&bpmp TEGRA186_RESET_UARTG>;
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reset-names = "serial";
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status = "disabled";
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};
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gpio_aon: gpio@c2f0000 {
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compatible = "nvidia,tegra186-gpio-aon";
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reg-names = "security", "gpio";
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reg = <0x0 0xc2f0000 0x0 0x1000>,
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<0x0 0xc2f1000 0x0 0x1000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pmc@c360000 {
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compatible = "nvidia,tegra186-pmc";
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reg = <0 0x0c360000 0 0x10000>,
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<0 0x0c370000 0 0x10000>,
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<0 0x0c380000 0 0x10000>,
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<0 0x0c390000 0 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch";
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};
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sysram@30000000 {
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compatible = "nvidia,tegra186-sysram", "mmio-sram";
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reg = <0x0 0x30000000 0x0 0x50000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
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cpu_bpmp_tx: shmem@4e000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4e000 0x0 0x1000>;
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label = "cpu-bpmp-tx";
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pool;
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};
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cpu_bpmp_rx: shmem@4f000 {
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compatible = "nvidia,tegra186-bpmp-shmem";
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reg = <0x0 0x4f000 0x0 0x1000>;
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label = "cpu-bpmp-rx";
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pool;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "nvidia,tegra186-denver", "arm,armv8";
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device_type = "cpu";
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reg = <0x000>;
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};
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cpu@1 {
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compatible = "nvidia,tegra186-denver", "arm,armv8";
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device_type = "cpu";
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reg = <0x001>;
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};
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cpu@2 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x100>;
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};
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cpu@3 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x101>;
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};
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cpu@4 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x102>;
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};
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cpu@5 {
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compatible = "arm,cortex-a57", "arm,armv8";
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device_type = "cpu";
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reg = <0x103>;
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};
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};
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bpmp: bpmp {
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compatible = "nvidia,tegra186-bpmp";
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
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TEGRA_HSP_DB_MASTER_BPMP>;
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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bpmp_i2c: i2c {
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compatible = "nvidia,tegra186-bpmp-i2c";
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nvidia,bpmp-bus-id = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
};
|