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This patch adds nds32 L2 cache controller binding documents. Signed-off-by: Greentime Hu <greentime@andestech.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
29 lines
941 B
Plaintext
29 lines
941 B
Plaintext
* Andestech L2 cache Controller
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The level-2 cache controller plays an important role in reducing memory latency
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for high performance systems, such as thoese designs with AndesCore processors.
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Level-2 cache controller in general enhances overall system performance
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signigicantly and the system power consumption might be reduced as well by
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reducing DRAM accesses.
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This binding specifies what properties must be available in the device tree
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representation of an Andestech L2 cache controller.
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Required properties:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: "andestech,atl2c"
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- reg : Physical base address and size of cache controller's memory mapped
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- cache-unified : Specifies the cache is a unified cache.
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- cache-level : Should be set to 2 for a level 2 cache.
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* Example
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cache-controller@e0500000 {
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compatible = "andestech,atl2c";
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reg = <0xe0500000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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