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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ec11ebcf2f
Set the default status for UARTs to disabled in the zynq-7000.dtsi file and let board dts files enable the UARTs on demand. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
121 lines
3.1 KiB
Plaintext
121 lines
3.1 KiB
Plaintext
/*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "xlnx,zynq-7000";
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 5 4>, <0 6 4>;
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interrupt-parent = <&intc>;
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reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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};
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xF8F02000 0x1000>;
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arm,data-latency = <2 3 2>;
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arm,tag-latency = <2 3 2>;
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cache-unified;
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cache-level = <2>;
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};
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uart0: uart@e0000000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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clocks = <&clkc 23>, <&clkc 40>;
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clock-names = "ref_clk", "aper_clk";
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reg = <0xE0000000 0x1000>;
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interrupts = <0 27 4>;
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};
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uart1: uart@e0001000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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clocks = <&clkc 24>, <&clkc 41>;
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clock-names = "ref_clk", "aper_clk";
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reg = <0xE0001000 0x1000>;
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interrupts = <0 50 4>;
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};
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slcr: slcr@f8000000 {
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compatible = "xlnx,zynq-slcr";
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reg = <0xF8000000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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clkc: clkc {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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};
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};
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};
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ttc0: ttc0@f8001000 {
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interrupt-parent = <&intc>;
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interrupts = < 0 10 4 0 11 4 0 12 4 >;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8001000 0x1000>;
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clock-ranges;
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};
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ttc1: ttc1@f8002000 {
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interrupt-parent = <&intc>;
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interrupts = < 0 37 4 0 38 4 0 39 4 >;
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compatible = "cdns,ttc";
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clocks = <&clkc 6>;
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reg = <0xF8002000 0x1000>;
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clock-ranges;
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};
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scutimer: scutimer@f8f00600 {
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interrupt-parent = <&intc>;
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interrupts = < 1 13 0x301 >;
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compatible = "arm,cortex-a9-twd-timer";
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reg = < 0xf8f00600 0x20 >;
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clocks = <&clkc 4>;
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} ;
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};
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};
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