mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 03:36:42 +07:00
56ce3ffbd5
This alters the local side address of the iospace to zero, non prefetchable memory local side address to 0x00000000 and prefetchable memory local side address to 0x10000000, so as to match the values actually poked in by the driver. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
115 lines
3.0 KiB
Plaintext
115 lines
3.0 KiB
Plaintext
/*
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* Device Tree for the ARM Integrator/AP platform
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*/
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/dts-v1/;
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/include/ "integrator.dtsi"
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/ {
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model = "ARM Integrator/AP";
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compatible = "arm,integrator-ap";
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aliases {
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arm,timer-primary = &timer2;
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arm,timer-secondary = &timer1;
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};
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
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};
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syscon {
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/* AP system controller registers */
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reg = <0x11000000 0x100>;
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};
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timer0: timer@13000000 {
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compatible = "arm,integrator-timer";
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};
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timer1: timer@13000100 {
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compatible = "arm,integrator-timer";
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};
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timer2: timer@13000200 {
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compatible = "arm,integrator-timer";
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};
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pic: pic@14000000 {
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valid-mask = <0x003fffff>;
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};
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pci: pciv3@62000000 {
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compatible = "v3,v360epc-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x62000000 0x10000>;
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interrupt-parent = <&pic>;
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interrupts = <17>; /* Bus error IRQ */
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ranges = <0x00000000 0 0x61000000 /* config space */
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0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
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0x01000000 0 0x0 /* I/O space */
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0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
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0x02000000 0 0x00000000 /* non-prefectable memory */
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0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
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0x42000000 0 0x10000000 /* prefetchable memory */
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0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map = <
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/* IDSEL 9 */
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0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
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0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
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0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
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0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
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/* IDSEL 10 */
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0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
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0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
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0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
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0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
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/* IDSEL 11 */
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0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
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0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
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0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
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0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
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/* IDSEL 12 */
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0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
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0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
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0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
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0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
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>;
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};
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fpga {
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/*
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* The Integator/AP predates the idea to have magic numbers
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* identifying the PrimeCell in hardware, thus we have to
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* supply these from the device tree.
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*/
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rtc: rtc@15000000 {
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compatible = "arm,pl030", "arm,primecell";
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arm,primecell-periphid = <0x00041030>;
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};
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uart0: uart@16000000 {
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compatible = "arm,pl010", "arm,primecell";
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arm,primecell-periphid = <0x00041010>;
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};
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uart1: uart@17000000 {
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compatible = "arm,pl010", "arm,primecell";
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arm,primecell-periphid = <0x00041010>;
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};
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kmi0: kmi@18000000 {
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compatible = "arm,pl050", "arm,primecell";
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arm,primecell-periphid = <0x00041050>;
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};
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kmi1: kmi@19000000 {
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compatible = "arm,pl050", "arm,primecell";
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arm,primecell-periphid = <0x00041050>;
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};
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};
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};
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