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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b5584b2bc2
The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
195 lines
3.7 KiB
Plaintext
195 lines
3.7 KiB
Plaintext
/*
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* Device Tree file for Marvell Armada XP evaluation board
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* (DB-78460-BP)
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/include/ "armada-xp-mv78460.dtsi"
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/ {
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model = "Marvell Armada XP Evaluation Board";
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compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
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chosen {
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bootargs = "console=ttyS0,115200 earlyprintk";
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};
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memory {
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device_type = "memory";
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reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
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};
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soc {
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ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
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0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
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0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
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internal-regs {
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serial@12000 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@12100 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@12200 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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serial@12300 {
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clock-frequency = <250000000>;
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status = "okay";
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};
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sata@a0000 {
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nr-ports = <2>;
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status = "okay";
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <25>;
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};
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phy3: ethernet-phy@3 {
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reg = <27>;
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};
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};
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ethernet@70000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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ethernet@74000 {
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status = "okay";
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phy = <&phy1>;
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phy-mode = "rgmii-id";
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};
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ethernet@30000 {
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status = "okay";
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phy = <&phy2>;
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phy-mode = "sgmii";
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};
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ethernet@34000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "sgmii";
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};
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins>;
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pinctrl-names = "default";
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status = "okay";
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/* No CD or WP GPIOs */
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broken-cd;
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};
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usb@50000 {
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status = "okay";
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};
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usb@51000 {
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status = "okay";
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};
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usb@52000 {
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status = "okay";
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};
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spi0: spi@10600 {
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "m25p64";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <20000000>;
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* All 6 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 0, Lane 2 */
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status = "okay";
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};
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pcie@4,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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devbus-bootcs@10400 {
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status = "okay";
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ranges = <0 0xf0000000 0x1000000>;
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/* Device Bus parameters are required */
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/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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/* NOR 16 MiB */
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nor@0 {
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compatible = "cfi-flash";
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reg = <0 0x1000000>;
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bank-width = <2>;
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};
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};
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};
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};
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};
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