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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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19f9a34f87
This implements initial support for the vsyscall page on SH. At the moment we leave it configurable due to having nommu to support from the same code base. We hook it up for the signal trampoline return at present, with more to be added later, once uClibc catches up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
135 lines
3.1 KiB
C
135 lines
3.1 KiB
C
/*
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* TLB flushing operations for SH with an MMU.
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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if (vma->vm_mm && vma->vm_mm->context.id != NO_CONTEXT) {
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unsigned long flags;
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unsigned long asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = vma->vm_mm->context.id & MMU_CONTEXT_ASID_MASK;
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page &= PAGE_MASK;
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local_irq_save(flags);
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if (vma->vm_mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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__flush_tlb_page(asid, page);
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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local_irq_restore(flags);
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}
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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if (mm->context.id != NO_CONTEXT) {
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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mm->context.id = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm);
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} else {
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unsigned long asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = mm->context.id & MMU_CONTEXT_ASID_MASK;
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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if (mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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while (start < end) {
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__flush_tlb_page(asid, start);
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start += PAGE_SIZE;
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}
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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flush_tlb_all();
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} else {
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unsigned long asid;
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unsigned long saved_asid = get_asid();
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asid = init_mm.context.id & MMU_CONTEXT_ASID_MASK;
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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set_asid(asid);
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while (start < end) {
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__flush_tlb_page(asid, start);
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start += PAGE_SIZE;
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}
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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/* Invalidate all TLB of this process. */
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/* Instead of invalidating each TLB, we get new MMU context. */
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if (mm->context.id != NO_CONTEXT) {
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unsigned long flags;
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local_irq_save(flags);
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mm->context.id = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm);
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local_irq_restore(flags);
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}
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}
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void flush_tlb_all(void)
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{
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unsigned long flags, status;
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/*
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* Flush all the TLB.
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*
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* Write to the MMU control register's bit:
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* TF-bit for SH-3, TI-bit for SH-4.
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* It's same position, bit #2.
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*/
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local_irq_save(flags);
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status = ctrl_inl(MMUCR);
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status |= 0x04;
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ctrl_outl(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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