mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 18:36:42 +07:00
f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
/*
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* include/asm-sh/cpu-sh3/timer.h
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*
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* Copyright (C) 2004 Lineo Solutions, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH3_TIMER_H
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#define __ASM_CPU_SH3_TIMER_H
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/*
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* ---------------------------------------------------------------------------
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* TMU Common definitions for SH3 processors
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* SH7706
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* SH7709S
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* SH7727
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* SH7729R
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* SH7710
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* SH7720
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* SH7710
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* ---------------------------------------------------------------------------
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*/
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU_TOCR 0xfffffe90 /* Byte access */
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU_012_TSTR 0xa412fe92 /* Byte access */
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#define TMU0_TCOR 0xa412fe94 /* Long access */
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#define TMU0_TCNT 0xa412fe98 /* Long access */
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#define TMU0_TCR 0xa412fe9c /* Word access */
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#define TMU1_TCOR 0xa412fea0 /* Long access */
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#define TMU1_TCNT 0xa412fea4 /* Long access */
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#define TMU1_TCR 0xa412fea8 /* Word access */
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#define TMU2_TCOR 0xa412feac /* Long access */
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#define TMU2_TCNT 0xa412feb0 /* Long access */
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#define TMU2_TCR 0xa412feb4 /* Word access */
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#else
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#define TMU_012_TSTR 0xfffffe92 /* Byte access */
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#define TMU0_TCOR 0xfffffe94 /* Long access */
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#define TMU0_TCNT 0xfffffe98 /* Long access */
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#define TMU0_TCR 0xfffffe9c /* Word access */
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#define TMU1_TCOR 0xfffffea0 /* Long access */
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#define TMU1_TCNT 0xfffffea4 /* Long access */
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#define TMU1_TCR 0xfffffea8 /* Word access */
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#define TMU2_TCOR 0xfffffeac /* Long access */
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#define TMU2_TCNT 0xfffffeb0 /* Long access */
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#define TMU2_TCR 0xfffffeb4 /* Word access */
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#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define TMU2_TCPR2 0xfffffeb8 /* Long access */
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#endif
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#endif
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#endif /* __ASM_CPU_SH3_TIMER_H */
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