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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d1160ebff1
Add initial clock configuration for display subsystem for Exynos5433 based TM2/TM2e boards in device tree in order to avoid dependency on the configuration left by the bootloader. This initial configuration is also needed to ensure that display subsystem is operational if display power domain gets turned off before clock controller is probed and the inital clock configuration left by the bootloader saved. TM2 and TM2e uses different rate for DISP PLL clock, but for better maintainability all 'assigned-clocks-*' properties for DISP CMU are defines in each board dts instead of redefining the rates property. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
66 lines
2.1 KiB
Plaintext
66 lines
2.1 KiB
Plaintext
/*
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* SAMSUNG Exynos5433 TM2E board device tree source
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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*
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* Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
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* Samsung Exynos5433 SoC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos5433-tm2-common.dtsi"
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/ {
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model = "Samsung TM2E board";
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compatible = "samsung,tm2e", "samsung,exynos5433";
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};
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&cmu_disp {
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/*
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* TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
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* clocks properties for DISP CMU for each board to keep them together
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* for easier review and maintenance.
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*/
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assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
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<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
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<&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
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<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
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<&cmu_disp CLK_MOUT_SCLK_DSIM0>,
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<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
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<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
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<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
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<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
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<&cmu_disp CLK_MOUT_DISP_PLL>,
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<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
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<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
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<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
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assigned-clock-parents = <0>, <0>,
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<&cmu_mif CLK_ACLK_DISP_333>,
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<&cmu_mif CLK_SCLK_DSIM0_DISP>,
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<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
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<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
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<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
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<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
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<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
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<&cmu_disp CLK_FOUT_DISP_PLL>,
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<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
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<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
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<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
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assigned-clock-rates = <278000000>, <400000000>;
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};
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&ldo31_reg {
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regulator-name = "TSP_VDD_1.8V_AP";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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&ldo38_reg {
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regulator-name = "VCC_3.3V_MOTOR_AP";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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