mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 11:07:39 +07:00
80820a7bc8
There are two USB3 host controllers on Hi3798CV200 SoC. This commit adds missing clocks for them. Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
83 lines
2.5 KiB
C
83 lines
2.5 KiB
C
/*
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* Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __DTS_HISTB_CLOCK_H
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#define __DTS_HISTB_CLOCK_H
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/* clocks provided by core CRG */
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#define HISTB_OSC_CLK 0
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#define HISTB_APB_CLK 1
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#define HISTB_AHB_CLK 2
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#define HISTB_UART1_CLK 3
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#define HISTB_UART2_CLK 4
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#define HISTB_UART3_CLK 5
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#define HISTB_I2C0_CLK 6
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#define HISTB_I2C1_CLK 7
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#define HISTB_I2C2_CLK 8
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#define HISTB_I2C3_CLK 9
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#define HISTB_I2C4_CLK 10
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#define HISTB_I2C5_CLK 11
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#define HISTB_SPI0_CLK 12
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#define HISTB_SPI1_CLK 13
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#define HISTB_SPI2_CLK 14
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#define HISTB_SCI_CLK 15
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#define HISTB_FMC_CLK 16
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#define HISTB_MMC_BIU_CLK 17
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#define HISTB_MMC_CIU_CLK 18
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#define HISTB_MMC_DRV_CLK 19
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#define HISTB_MMC_SAMPLE_CLK 20
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#define HISTB_SDIO0_BIU_CLK 21
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#define HISTB_SDIO0_CIU_CLK 22
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#define HISTB_SDIO0_DRV_CLK 23
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#define HISTB_SDIO0_SAMPLE_CLK 24
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#define HISTB_PCIE_AUX_CLK 25
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#define HISTB_PCIE_PIPE_CLK 26
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#define HISTB_PCIE_SYS_CLK 27
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#define HISTB_PCIE_BUS_CLK 28
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#define HISTB_ETH0_MAC_CLK 29
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#define HISTB_ETH0_MACIF_CLK 30
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#define HISTB_ETH1_MAC_CLK 31
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#define HISTB_ETH1_MACIF_CLK 32
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#define HISTB_COMBPHY1_CLK 33
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#define HISTB_USB2_BUS_CLK 34
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#define HISTB_USB2_PHY_CLK 35
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#define HISTB_USB2_UTMI_CLK 36
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#define HISTB_USB2_12M_CLK 37
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#define HISTB_USB2_48M_CLK 38
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#define HISTB_USB2_OTG_UTMI_CLK 39
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#define HISTB_USB2_PHY1_REF_CLK 40
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#define HISTB_USB2_PHY2_REF_CLK 41
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#define HISTB_COMBPHY0_CLK 42
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#define HISTB_USB3_BUS_CLK 43
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#define HISTB_USB3_UTMI_CLK 44
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#define HISTB_USB3_PIPE_CLK 45
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#define HISTB_USB3_SUSPEND_CLK 46
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#define HISTB_USB3_BUS_CLK1 47
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#define HISTB_USB3_UTMI_CLK1 48
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#define HISTB_USB3_PIPE_CLK1 49
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#define HISTB_USB3_SUSPEND_CLK1 50
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/* clocks provided by mcu CRG */
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#define HISTB_MCE_CLK 1
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#define HISTB_IR_CLK 2
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#define HISTB_TIMER01_CLK 3
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#define HISTB_LEDC_CLK 4
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#define HISTB_UART0_CLK 5
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#define HISTB_LSADC_CLK 6
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#endif /* __DTS_HISTB_CLOCK_H */
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