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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1ccd653c30
This adds a basic dtsi for MT8127 SoC. Signed-off-by: Joe.C <yingjoe.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
95 lines
2.1 KiB
Plaintext
95 lines
2.1 KiB
Plaintext
/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Joe.C <yingjoe.chen@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton64.dtsi"
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/ {
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compatible = "mediatek,mt8127";
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x3>;
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};
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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timer: timer@10008000 {
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compatible = "mediatek,mt8127-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a7-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x1000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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};
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};
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