mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 03:57:27 +07:00
b3345d7c57
This is the bulk of new SoC enablement and other platform changes for 3.17:
* Samsung S5PV210 has been converted to DT and multiplatform
* Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
* Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood.
* Hwmod data for TI AM43xx and DRA7 platforms.
* More additions of Renesas shmobile platform support
* Removal of plat-samsung contents that can be removed with S5PV210 being
multiplatform/DT-enabled and the other two old platforms being removed.
New platforms (most with only basic support right now):
* Hisilicon X5HD2 settop box chipset is introduced
* Mediatek MT6589 (mobile chipset) is introduced
* Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJT5Dp+AAoJEIwa5zzehBx3w1sP/0vjT/LQOmC8Lv8RW2Ley2ua
hNu3HcNPnT/N40JEdU9YNv3q0fdxGgcfKj011CNN+49zPSUf1xduk2wfCAk9yV50
8Sbt1PfDGm1YyUugGN420CzI431pPoM1OGXHZHkAmg+2J286RtUi3NckB//QDbCY
QhEjhpYc9SXhAOCGwmB4ab7thOljOFSPzKTLMTu3+PNI5zRPRgkDkt6w9XlsAYmB
nuR271BnzsROkMzAjycwaJ3kdim7wqrMRfk8g96o0jHSF5qf4zsT5uWYYAjTxdUQ
8Ajz6zjeHe4+95TwTDcq+lCX6rDLZgwkvCAc6hFbeg0uR7Dyek0h6XMEYtwdjaiU
KNPwOENrYdENNDAGRpkFp1x4h/rY9Plfru0bBo5o6t7aPBvmNeCDzRtlTtLiUNDV
dG8sfDMtrS/wFHVjylDSQ60Mb+wuW0XneC8D7chY/iRhIllUYi6YXXvt+/tH5C20
oYDOWqqcDFSb0sJhE5pn4KBV82ZaHx9jMBWGLl+erg2sDX/SK8SxOkLqKYZKtKB5
0leOGE3Y+C70xt3G9HftLz2sAvvt+C8UPsApPT+dHNE401TWJOYx6LphPkQKjeeK
P1iwKi+It3l+FaBypgJy/LeMQRy7EyvDBK2I5WoVL/R2qq14EmP1ui3Tthjj0bhq
tBBof6P9c8OnRVj1Lz3R
=5TJ6
-----END PGP SIGNATURE-----
Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This is the bulk of new SoC enablement and other platform changes for
3.17:
- Samsung S5PV210 has been converted to DT and multiplatform
- Clock drivers and bindings for some of the lower-end i.MX 1/2
platforms
- Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood
- Hwmod data for TI AM43xx and DRA7 platforms
- More additions of Renesas shmobile platform support
- Removal of plat-samsung contents that can be removed with S5PV210
being multiplatform/DT-enabled and the other two old platforms
being removed
New platforms (most with only basic support right now):
- Hisilicon X5HD2 settop box chipset is introduced
- Mediatek MT6589 (mobile chipset) is introduced
- Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code"
* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
ARM: hisi: remove smp from machine descriptor
power: reset: move hisilicon reboot code
ARM: dts: Add hix5hd2-dkb dts file.
ARM: debug: Rename Hi3716 to HIX5HD2
ARM: hisi: enable hix5hd2 SoC
ARM: hisi: add ARCH_HISI
MAINTAINERS: add entry for Broadcom ARM STB architecture
ARM: brcmstb: select GISB arbiter and interrupt drivers
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
ARM: configs: enable SMP in bcm_defconfig
ARM: add SMP support for Broadcom mobile SoCs
Documentation: arm: misc updates to Marvell EBU SoC status
Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
ARM: mvebu: fix build without platforms selected
ARM: mvebu: add cpuidle support for Armada 38x
ARM: mvebu: add cpuidle support for Armada 370
cpuidle: mvebu: add Armada 38x support
cpuidle: mvebu: add Armada 370 support
cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
ARM: mvebu: export the SCU address
...
567 lines
14 KiB
Plaintext
567 lines
14 KiB
Plaintext
/*
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* Hisilicon Ltd. Hi3620 SoC
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*
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* Copyright (C) 2012-2013 Hisilicon Ltd.
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* Copyright (C) 2012-2013 Linaro Ltd.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/hi3620-clock.h>
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/ {
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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pclk: clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "apb_pclk";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "hisilicon,hi3620-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0x0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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amba {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,amba-bus";
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interrupt-parent = <&gic>;
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ranges = <0 0xfc000000 0x2000000>;
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x100000 0x100000>;
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interrupts = <0 15 4>;
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cache-unified;
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cache-level = <2>;
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};
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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/* gic dist base, gic cpu base */
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reg = <0x1000 0x1000>, <0x100 0x100>;
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};
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sysctrl: system-controller@802000 {
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compatible = "hisilicon,sysctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x802000 0x1000>;
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reg = <0x802000 0x1000>;
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smp-offset = <0x31c>;
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resume-offset = <0x308>;
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reboot-offset = <0x4>;
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clock: clock@0 {
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compatible = "hisilicon,hi3620-clock";
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reg = <0 0x10000>;
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#clock-cells = <1>;
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};
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};
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dual_timer0: dual_timer@800000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x800000 0x1000>;
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/* timer00 & timer01 */
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interrupts = <0 0 4>, <0 1 4>;
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clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dual_timer1: dual_timer@801000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x801000 0x1000>;
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/* timer10 & timer11 */
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interrupts = <0 2 4>, <0 3 4>;
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clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dual_timer2: dual_timer@a01000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0xa01000 0x1000>;
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/* timer20 & timer21 */
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interrupts = <0 4 4>, <0 5 4>;
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clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dual_timer3: dual_timer@a02000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0xa02000 0x1000>;
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/* timer30 & timer31 */
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interrupts = <0 6 4>, <0 7 4>;
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clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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dual_timer4: dual_timer@a03000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0xa03000 0x1000>;
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/* timer40 & timer41 */
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interrupts = <0 96 4>, <0 97 4>;
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clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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timer5: timer@600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x600 0x20>;
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interrupts = <1 13 0xf01>;
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};
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uart0: uart@b00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb00000 0x1000>;
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interrupts = <0 20 4>;
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clocks = <&clock HI3620_UARTCLK0>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart1: uart@b01000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb01000 0x1000>;
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interrupts = <0 21 4>;
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clocks = <&clock HI3620_UARTCLK1>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart2: uart@b02000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb02000 0x1000>;
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interrupts = <0 22 4>;
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clocks = <&clock HI3620_UARTCLK2>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart3: uart@b03000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb03000 0x1000>;
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interrupts = <0 23 4>;
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clocks = <&clock HI3620_UARTCLK3>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart4: uart@b04000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xb04000 0x1000>;
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interrupts = <0 24 4>;
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clocks = <&clock HI3620_UARTCLK4>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio0: gpio@806000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x806000 0x1000>;
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interrupts = <0 64 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
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&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK0>;
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clock-names = "apb_pclk";
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};
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gpio1: gpio@807000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x807000 0x1000>;
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interrupts = <0 65 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
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&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
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&pmx0 6 5 1 &pmx0 7 6 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK1>;
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clock-names = "apb_pclk";
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};
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gpio2: gpio@808000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x808000 0x1000>;
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interrupts = <0 66 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
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&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
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&pmx0 6 3 1 &pmx0 7 3 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK2>;
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clock-names = "apb_pclk";
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};
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gpio3: gpio@809000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x809000 0x1000>;
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interrupts = <0 67 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
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&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
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&pmx0 6 11 1 &pmx0 7 11 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK3>;
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clock-names = "apb_pclk";
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};
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gpio4: gpio@80a000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x80a000 0x1000>;
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interrupts = <0 68 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
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&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
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&pmx0 6 13 1 &pmx0 7 13 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK4>;
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clock-names = "apb_pclk";
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};
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gpio5: gpio@80b000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x80b000 0x1000>;
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interrupts = <0 69 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
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&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
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&pmx0 6 16 1 &pmx0 7 16 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK5>;
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clock-names = "apb_pclk";
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};
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gpio6: gpio@80c000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x80c000 0x1000>;
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interrupts = <0 70 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
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&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
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&pmx0 6 18 1 &pmx0 7 19 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK6>;
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clock-names = "apb_pclk";
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};
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gpio7: gpio@80d000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x80d000 0x1000>;
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interrupts = <0 71 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
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&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
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&pmx0 6 25 1 &pmx0 7 26 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK7>;
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clock-names = "apb_pclk";
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};
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gpio8: gpio@80e000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x80e000 0x1000>;
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interrupts = <0 72 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
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&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
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&pmx0 6 33 1 &pmx0 7 34 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK8>;
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clock-names = "apb_pclk";
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};
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gpio9: gpio@80f000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x80f000 0x1000>;
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interrupts = <0 73 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
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&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
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&pmx0 6 41 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK9>;
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clock-names = "apb_pclk";
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};
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gpio10: gpio@810000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x810000 0x1000>;
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interrupts = <0 74 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
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&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK10>;
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clock-names = "apb_pclk";
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};
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gpio11: gpio@811000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x811000 0x1000>;
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interrupts = <0 75 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
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&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
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&pmx0 6 49 1 &pmx0 7 49 1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&clock HI3620_GPIOCLK11>;
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clock-names = "apb_pclk";
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};
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gpio12: gpio@812000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x812000 0x1000>;
|
|
interrupts = <0 76 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
|
|
&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
|
|
&pmx0 6 51 1 &pmx0 7 52 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK12>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio13: gpio@813000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x813000 0x1000>;
|
|
interrupts = <0 77 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
|
|
&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
|
|
&pmx0 6 55 1 &pmx0 7 56 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK13>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio14: gpio@814000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x814000 0x1000>;
|
|
interrupts = <0 78 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
|
|
&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
|
|
&pmx0 6 60 1 &pmx0 7 61 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK14>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio15: gpio@815000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x815000 0x1000>;
|
|
interrupts = <0 79 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
|
|
&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
|
|
&pmx0 6 64 1 &pmx0 7 65 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK15>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio16: gpio@816000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x816000 0x1000>;
|
|
interrupts = <0 80 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
|
|
&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
|
|
&pmx0 6 72 1 &pmx0 7 73 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK16>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio17: gpio@817000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x817000 0x1000>;
|
|
interrupts = <0 81 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
|
|
&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
|
|
&pmx0 6 80 1 &pmx0 7 81 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK17>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio18: gpio@818000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x818000 0x1000>;
|
|
interrupts = <0 82 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
|
|
&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
|
|
&pmx0 6 86 1 &pmx0 7 87 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK18>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio19: gpio@819000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x819000 0x1000>;
|
|
interrupts = <0 83 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
|
|
&pmx0 3 88 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK19>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio20: gpio@81a000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x81a000 0x1000>;
|
|
interrupts = <0 84 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
|
|
&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK20>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
gpio21: gpio@81b000 {
|
|
compatible = "arm,pl061", "arm,primecell";
|
|
reg = <0x81b000 0x1000>;
|
|
interrupts = <0 85 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&clock HI3620_GPIOCLK21>;
|
|
clock-names = "apb_pclk";
|
|
};
|
|
|
|
pmx0: pinmux@803000 {
|
|
compatible = "pinctrl-single";
|
|
reg = <0x803000 0x188>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
#gpio-range-cells = <3>;
|
|
ranges;
|
|
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <7>;
|
|
/* pin base, nr pins & gpio function */
|
|
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
|
|
&range 12 1 0 &range 13 29 1
|
|
&range 43 1 0 &range 44 49 1
|
|
&range 94 1 1 &range 96 2 1>;
|
|
|
|
range: gpio-range {
|
|
#pinctrl-single,gpio-range-cells = <3>;
|
|
};
|
|
};
|
|
|
|
pmx1: pinmux@803800 {
|
|
compatible = "pinconf-single";
|
|
reg = <0x803800 0x2dc>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pinctrl-single,register-width = <32>;
|
|
};
|
|
};
|
|
};
|