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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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23beb1adb5
add nodes for NOR flash, parallel Nand flash with error correction code support. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Cc: RogerCC Lin <rogercc.lin@mediatek.com> Cc: Guochun Mao <guochun.mao@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
560 lines
13 KiB
Plaintext
560 lines
13 KiB
Plaintext
/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Ming Huang <ming.huang@mediatek.com>
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* Sean Wang <sean.wang@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <dt-bindings/power/mt7622-power.h>
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#include <dt-bindings/reset/mt7622-reset.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "mediatek,mt7622";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-300000000 {
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opp-hz = /bits/ 64 <30000000>;
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opp-microvolt = <950000>;
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};
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opp-437500000 {
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opp-hz = /bits/ 64 <437500000>;
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opp-microvolt = <1000000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1050000>;
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};
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opp-812500000 {
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opp-hz = /bits/ 64 <812500000>;
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opp-microvolt = <1100000>;
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};
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opp-1025000000 {
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opp-hz = /bits/ 64 <1025000000>;
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opp-microvolt = <1150000>;
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};
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opp-1137500000 {
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opp-hz = /bits/ 64 <1137500000>;
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opp-microvolt = <1200000>;
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};
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opp-1262500000 {
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opp-hz = /bits/ 64 <1262500000>;
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opp-microvolt = <1250000>;
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};
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opp-1350000000 {
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opp-hz = /bits/ 64 <1350000000>;
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opp-microvolt = <1310000>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
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<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table>;
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#cooling-cells = <2>;
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enable-method = "psci";
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clock-frequency = <1300000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
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<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
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clock-names = "cpu", "intermediate";
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operating-points-v2 = <&cpu_opp_table>;
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enable-method = "psci";
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clock-frequency = <1300000000>;
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};
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};
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pwrap_clk: dummy40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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};
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clk25m: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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clock-output-names = "clkxtal";
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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no-map;
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};
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <1000>;
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thermal-sensors = <&thermal 0>;
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trips {
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cpu_passive: cpu-passive {
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temperature = <47000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_active: cpu-active {
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temperature = <67000>;
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hysteresis = <2000>;
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type = "active";
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};
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cpu_hot: cpu-hot {
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temperature = <87000>;
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hysteresis = <2000>;
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type = "hot";
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};
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cpu-crit {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_passive>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map1 {
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trip = <&cpu_active>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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map2 {
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trip = <&cpu_hot>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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infracfg: infracfg@10000000 {
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compatible = "mediatek,mt7622-infracfg",
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"syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pwrap: pwrap@10001000 {
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compatible = "mediatek,mt7622-pwrap";
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reg = <0 0x10001000 0 0x250>;
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reg-names = "pwrap";
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clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
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clock-names = "spi", "wrap";
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resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
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reset-names = "pwrap";
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pericfg: pericfg@10002000 {
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compatible = "mediatek,mt7622-pericfg",
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"syscon";
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reg = <0 0x10002000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt7622-scpsys",
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"syscon";
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#power-domain-cells = <1>;
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reg = <0 0x10006000 0 0x1000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
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infracfg = <&infracfg>;
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clocks = <&topckgen CLK_TOP_HIF_SEL>;
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clock-names = "hif_sel";
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};
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cir: cir@10009000 {
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compatible = "mediatek,mt7622-cir";
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reg = <0 0x10009000 0 0x1000>;
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interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_IRRX_PD>,
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<&topckgen CLK_TOP_AXI_SEL>;
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clock-names = "clk", "bus";
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status = "disabled";
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};
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sysirq: interrupt-controller@10200620 {
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compatible = "mediatek,mt7622-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200620 0 0x20>;
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};
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efuse: efuse@10206000 {
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compatible = "mediatek,mt7622-efuse",
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"mediatek,efuse";
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reg = <0 0x10206000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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thermal_calibration: calib@198 {
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reg = <0x198 0xc>;
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};
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};
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt7622-apmixedsys",
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"syscon";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: topckgen@10210000 {
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compatible = "mediatek,mt7622-topckgen",
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"syscon";
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reg = <0 0x10210000 0 0x1000>;
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#clock-cells = <1>;
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};
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rng: rng@1020f000 {
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compatible = "mediatek,mt7622-rng",
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"mediatek,mt7623-rng";
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reg = <0 0x1020f000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_TRNG>;
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clock-names = "rng";
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};
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pio: pinctrl@10211000 {
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compatible = "mediatek,mt7622-pinctrl";
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reg = <0 0x10211000 0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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watchdog: watchdog@10212000 {
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compatible = "mediatek,mt7622-wdt",
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"mediatek,mt6589-wdt";
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reg = <0 0x10212000 0 0x800>;
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};
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rtc: rtc@10212800 {
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compatible = "mediatek,mt7622-rtc",
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"mediatek,soc-rtc";
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reg = <0 0x10212800 0 0x200>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_RTC>;
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clock-names = "rtc";
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};
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gic: interrupt-controller@10300000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10310000 0 0x1000>,
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<0 0x10320000 0 0x1000>,
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<0 0x10340000 0 0x2000>,
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<0 0x10360000 0 0x2000>;
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};
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auxadc: adc@11001000 {
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compatible = "mediatek,mt7622-auxadc";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&pericfg CLK_PERI_AUXADC_PD>;
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clock-names = "main";
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#io-channel-cells = <1>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7622-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART1_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7622-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART1_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7622-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART2_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11005000 {
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compatible = "mediatek,mt7622-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11005000 0 0x400>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&pericfg CLK_PERI_UART3_PD>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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pwm: pwm@11006000 {
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compatible = "mediatek,mt7622-pwm";
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reg = <0 0x11006000 0 0x1000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM_PD>,
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<&pericfg CLK_PERI_PWM1_PD>,
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<&pericfg CLK_PERI_PWM2_PD>,
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<&pericfg CLK_PERI_PWM3_PD>,
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<&pericfg CLK_PERI_PWM4_PD>,
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<&pericfg CLK_PERI_PWM5_PD>,
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<&pericfg CLK_PERI_PWM6_PD>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
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"pwm5", "pwm6";
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt7622-i2c";
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reg = <0 0x11007000 0 0x90>,
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<0 0x11000100 0 0x80>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C0_PD>,
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<&pericfg CLK_PERI_AP_DMA_PD>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt7622-i2c";
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reg = <0 0x11008000 0 0x90>,
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<0 0x11000180 0 0x80>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1_PD>,
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<&pericfg CLK_PERI_AP_DMA_PD>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt7622-i2c";
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reg = <0 0x11009000 0 0x90>,
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<0 0x11000200 0 0x80>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2_PD>,
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<&pericfg CLK_PERI_AP_DMA_PD>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7622-spi";
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
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<&topckgen CLK_TOP_SPI0_SEL>,
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<&pericfg CLK_PERI_SPI0_PD>;
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clock-names = "parent-clk", "sel-clk", "spi-clk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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thermal: thermal@1100b000 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7622-thermal";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_THERM_PD>,
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<&pericfg CLK_PERI_AUXADC_PD>;
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clock-names = "therm", "auxadc";
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resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
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reset-names = "therm";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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};
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btif: serial@1100c000 {
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compatible = "mediatek,mt7622-btif",
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"mediatek,mtk-btif";
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reg = <0 0x1100c000 0 0x1000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_BTIF_PD>;
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clock-names = "main";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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nandc: nfi@1100d000 {
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compatible = "mediatek,mt7622-nfc";
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reg = <0 0x1100D000 0 0x1000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_PD>,
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<&pericfg CLK_PERI_SNFI_PD>;
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clock-names = "nfi_clk", "pad_clk";
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ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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|
bch: ecc@1100e000 {
|
|
compatible = "mediatek,mt7622-ecc";
|
|
reg = <0 0x1100e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&pericfg CLK_PERI_NFIECC_PD>;
|
|
clock-names = "nfiecc_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
nor_flash: spi@11014000 {
|
|
compatible = "mediatek,mt7622-nor",
|
|
"mediatek,mt8173-nor";
|
|
reg = <0 0x11014000 0 0xe0>;
|
|
clocks = <&pericfg CLK_PERI_FLASH_PD>,
|
|
<&topckgen CLK_TOP_FLASH_SEL>;
|
|
clock-names = "spi", "sf";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@11016000 {
|
|
compatible = "mediatek,mt7622-spi";
|
|
reg = <0 0x11016000 0 0x100>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI1_SEL>,
|
|
<&pericfg CLK_PERI_SPI1_PD>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@11019000 {
|
|
compatible = "mediatek,mt7622-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11019000 0 0x400>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_UART_SEL>,
|
|
<&pericfg CLK_PERI_UART4_PD>;
|
|
clock-names = "baud", "bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
ssusbsys: ssusbsys@1a000000 {
|
|
compatible = "mediatek,mt7622-ssusbsys",
|
|
"syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pciesys: pciesys@1a100800 {
|
|
compatible = "mediatek,mt7622-pciesys",
|
|
"syscon";
|
|
reg = <0 0x1a100800 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
ethsys: syscon@1b000000 {
|
|
compatible = "mediatek,mt7622-ethsys",
|
|
"syscon";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
sgmiisys: sgmiisys@1b128000 {
|
|
compatible = "mediatek,mt7622-sgmiisys",
|
|
"syscon";
|
|
reg = <0 0x1b128000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|