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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1f2e25b2d5
More consolidation of our MSR available bit handling. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
185 lines
4.6 KiB
ArmAsm
185 lines
4.6 KiB
ArmAsm
/*
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* FPU support code, moved here from head.S so that it can be used
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* by chips which use other head-whatever.S files.
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Copyright (C) 1996 Paul Mackerras.
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* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#ifdef CONFIG_VSX
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#define __REST_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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#define __SAVE_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS(n,base); \
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b 3f; \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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#endif
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#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
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#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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/* void do_load_up_transact_fpu(struct thread_struct *thread)
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*
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* This is similar to load_up_fpu but for the transactional version of the FP
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* register set. It doesn't mess with the task MSR or valid flags.
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* Furthermore, we don't do lazy FP with TM currently.
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*/
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_GLOBAL(do_load_up_transact_fpu)
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mfmsr r6
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ori r5,r6,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC
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MTMSRD(r5)
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addi r7,r3,THREAD_TRANSACT_FPSTATE
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lfd fr0,FPSTATE_FPSCR(r7)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R7)
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blr
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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/*
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* Load state from memory into FP registers including FPSCR.
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(load_fp_state)
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lfd fr0,FPSTATE_FPSCR(r3)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R3)
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blr
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/*
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* Store FP state into memory, including FPSCR
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(store_fp_state)
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SAVE_32FPVSRS(0, R4, R3)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r3)
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blr
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Load up this task's FP registers from its thread_struct,
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* enable the FPU for the current task and return to the task.
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* Note that on 32-bit this can only use registers that will be
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* restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
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*/
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_GLOBAL(load_up_fpu)
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mfmsr r5
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ori r5,r5,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC
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MTMSRD(r5) /* enable use of fpu now */
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isync
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/* enable use of FP after return */
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#ifdef CONFIG_PPC32
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mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r9,r9,MSR_FP /* enable FP for current */
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or r9,r9,r4
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#else
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r12,r12,MSR_FP
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or r12,r12,r4
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std r12,_MSR(r1)
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#endif
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addi r10,r5,THREAD_FPSTATE
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lfd fr0,FPSTATE_FPSCR(r10)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R10)
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/* restore registers and return */
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/* we haven't used ctr or xer or lr */
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blr
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/*
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* __giveup_fpu(tsk)
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* Disable FP for the task given as the argument,
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* and save the floating-point registers in its thread_struct.
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* Enables the FPU for use in the kernel on return.
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*/
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_GLOBAL(__giveup_fpu)
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addi r3,r3,THREAD /* want THREAD of task */
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PPC_LL r6,THREAD_FPSAVEAREA(r3)
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PPC_LL r5,PT_REGS(r3)
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PPC_LCMPI 0,r6,0
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bne 2f
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addi r6,r3,THREAD_FPSTATE
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2: PPC_LCMPI 0,r5,0
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SAVE_32FPVSRS(0, R4, R6)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r6)
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beq 1f
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PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r3,MSR_FP|MSR_FE0|MSR_FE1
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r3,r3,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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andc r4,r4,r3 /* disable FP for previous task */
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PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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blr
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/*
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* These are used in the alignment trap handler when emulating
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* single-precision loads and stores.
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*/
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_GLOBAL(cvt_fd)
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lfs 0,0(r3)
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stfd 0,0(r4)
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blr
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_GLOBAL(cvt_df)
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lfd 0,0(r3)
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stfs 0,0(r4)
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blr
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