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AM335x and AM437x support various low power modes as documented in section 8.1.4.3 of the AM335x Technical Reference Manual and section 6.4.3 of the AM437x Technical Reference Manual. DeepSleep0 mode offers the lowest power mode with limited wakeup sources without a system reboot and is mapped as the suspend state in the kernel. In this state, MPU and PER domains are turned off with the internal RAM held in retention to facilitate the resume process. As part of the boot process, the assembly code is copied over to OCMCRAM so it can be executed to turn of the EMIF and put DDR into self refresh. Both platforms have a Cortex-M3 (WKUP_M3) which assists the MPU in DeepSleep0 entry and exit. WKUP_M3 takes care of the clockdomain and powerdomain transitions based on the intended low power state. MPU needs to load the appropriate WKUP_M3 binary onto the WKUP_M3 memory space before it can leverage any of the PM features like DeepSleep. This loading is handled by the remoteproc driver wkup_m3_rproc. Communication with the WKUP_M3 is handled by a wkup_m3_ipc driver that exposes the specific PM functionality to be used the PM code. In the current implementation when the suspend process is initiated, MPU interrupts the WKUP_M3 to let it know about the intent of entering DeepSleep0 and waits for an ACK. When the ACK is received MPU continues with its suspend process to suspend all the drivers and then jumps to assembly in OCMC RAM. The assembly code puts the external RAM in self-refresh mode, gates the MPU clock, and then finally executes the WFI instruction. Execution of the WFI instruction with MPU clock gated triggers another interrupt to the WKUP_M3 which then continues with the power down sequence wherein the clockdomain and powerdomain transition takes place. As part of the sleep sequence, WKUP_M3 unmasks the interrupt lines for the wakeup sources. WFI execution on WKUP_M3 causes the hardware to disable the main oscillator of the SoC and from here system remains in sleep state until a wake source brings the system into resume path. When a wakeup event occurs, WKUP_M3 starts the power-up sequence by switching on the power domains and finally enabling the clock to MPU. Since the MPU gets powered down as part of the sleep sequence in the resume path ROM code starts executing. The ROM code detects a wakeup from sleep and then jumps to the resume location in OCMC which was populated in one of the IPC registers as part of the suspend sequence. Code is based on work by Vaibhav Bedia. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
55 lines
1.2 KiB
Plaintext
55 lines
1.2 KiB
Plaintext
* TI - MPU (Main Processor Unit) subsystem
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The MPU subsystem contain one or several ARM cores
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depending of the version.
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The MPU contain CPUs, GIC, L2 cache and a local PRCM.
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Required properties:
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- compatible : Should be "ti,omap3-mpu" for OMAP3
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Should be "ti,omap4-mpu" for OMAP4
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Should be "ti,omap5-mpu" for OMAP5
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- ti,hwmods: "mpu"
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Optional properties:
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- sram: Phandle to the ocmcram node
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am335x and am437x only:
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- pm-sram: Phandles to ocmcram nodes to be used for power management.
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First should be type 'protect-exec' for the driver to use to copy
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and run PM functions, second should be regular pool to be used for
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data region for code. See Documentation/devicetree/bindings/sram/sram.txt
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for more details.
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Examples:
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- For an OMAP5 SMP system:
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu"
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};
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- For an OMAP4 SMP system:
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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};
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- For an OMAP3 monocore system:
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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};
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- For an AM335x system:
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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pm-sram = <&pm_sram_code
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&pm_sram_data>;
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};
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