mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
e7309c2673
The L3 Error handling on OMAP5 for the most part is very similar
to that of OMAP4, and had leveraged common data structures and
register layout definitions so far. Upon closer inspection, there
are a few minor differences causing an incorrect decoding and
reporting of the master NIU upon an error:
1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies
11 bits on OMAP5 as against 8 bits on OMAP4, with the master
NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR
field.
2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3
input sources on OMAP5. The common DEBUGSS source is at a
different input on each SoC.
Fix the above issues by using a OMAP5-specific compatible property
and using SoC-specific data where there are differences.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
24 lines
719 B
Plaintext
24 lines
719 B
Plaintext
* TI - L3 Network On Chip (NoC)
|
|
|
|
This version is an implementation of the generic NoC IP
|
|
provided by Arteris.
|
|
|
|
Required properties:
|
|
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
|
|
Should be "ti,omap4-l3-noc" for OMAP4 family
|
|
Should be "ti,omap5-l3-noc" for OMAP5 family
|
|
Should be "ti,dra7-l3-noc" for DRA7 family
|
|
Should be "ti,am4372-l3-noc" for AM43 family
|
|
- reg: Contains L3 register address range for each noc domain.
|
|
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
|
|
|
|
Examples:
|
|
|
|
ocp {
|
|
compatible = "ti,omap4-l3-noc", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
|
};
|