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Nearly each Baikal-T1 IP-core is supposed to have a clock source of particular frequency. But since there are greater than five IP-blocks embedded into the SoC, the CCU PLLs can't fulfill all the needs. Baikal-T1 CCU provides a set of fixed and configurable clock dividers in order to generate a necessary signal for each chip sub-block. This driver creates the of-based hardware clocks for each divider available in Baikal-T1 CCU. The same way as for PLLs we split the functionality up into the clocks operations (gate, ungate, set rate, etc) and hardware clocks declaration/registration procedures. In accordance with the CCU documentation all its dividers are distributed into two CCU sub-blocks: AXI-bus and system devices reference clocks. The former sub-block is used to supply the clocks for AXI-bus interfaces (AXI clock domains) and the later one provides the SoC IP-cores reference clocks. Each sub-block is represented by a dedicated DT node, so they have different compatible strings to distinguish one from another. For some reason CCU provides the dividers of different types. Some dividers can be gateable some can't, some are fixed while the others are variable, some have special divider' limitations, some've got a non-standard register layout and so on. In order to cover all of these cases the hardware clocks driver is designed with an info-descriptor pattern. So there are special static descriptors declared for the dividers of each type with additional flags describing the block peculiarity. These descriptors are then used to create hardware clocks with proper operations. Some CCU dividers provide a way to reset a domain they generate a clock for. So the CCU AXI-bus and CCU system devices clock drivers also perform the reset controller registration. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20200526222056.18072-5-Sergey.Semin@baikalelectronics.ru [sboyd@kernel.org: Drop return from void function, silence sparse warnings about initializing structs with NULL vs. integer] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
111 lines
3.0 KiB
C
111 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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*
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* Baikal-T1 CCU Dividers interface driver
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*/
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#ifndef __CLK_BT1_CCU_DIV_H__
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#define __CLK_BT1_CCU_DIV_H__
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/bits.h>
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#include <linux/of.h>
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/*
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* CCU Divider private flags
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* @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
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* It can be 0 though, which is functionally the same.
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* @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
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* It can be either 0 or greater than 3.
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* @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
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* @CCU_DIV_RESET_DOMAIN: Provide reset clock domain method.
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*/
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#define CCU_DIV_SKIP_ONE BIT(1)
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#define CCU_DIV_SKIP_ONE_TO_THREE BIT(2)
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#define CCU_DIV_LOCK_SHIFTED BIT(3)
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#define CCU_DIV_RESET_DOMAIN BIT(4)
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/*
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* enum ccu_div_type - CCU Divider types
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* @CCU_DIV_VAR: Clocks gate with variable divider.
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* @CCU_DIV_GATE: Clocks gate with fixed divider.
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* @CCU_DIV_FIXED: Ungateable clock with fixed divider.
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*/
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enum ccu_div_type {
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CCU_DIV_VAR,
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CCU_DIV_GATE,
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CCU_DIV_FIXED
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};
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/*
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* struct ccu_div_init_data - CCU Divider initialization data
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* @id: Clocks private identifier.
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* @name: Clocks name.
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* @parent_name: Parent clocks name in a fw node.
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* @base: Divider register base address with respect to the sys_regs base.
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* @sys_regs: Baikal-T1 System Controller registers map.
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* @np: Pointer to the node describing the CCU Dividers.
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* @type: CCU divider type (variable, fixed with and without gate).
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* @width: Divider width if it's variable.
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* @divider: Divider fixed value.
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* @flags: CCU Divider clock flags.
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* @features: CCU Divider private features.
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*/
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struct ccu_div_init_data {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned int base;
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struct regmap *sys_regs;
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struct device_node *np;
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enum ccu_div_type type;
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union {
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unsigned int width;
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unsigned int divider;
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};
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unsigned long flags;
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unsigned long features;
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};
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/*
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* struct ccu_div - CCU Divider descriptor
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* @hw: clk_hw of the divider.
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* @id: Clock private identifier.
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* @reg_ctl: Divider control register base address.
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* @sys_regs: Baikal-T1 System Controller registers map.
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* @lock: Divider state change spin-lock.
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* @mask: Divider field mask.
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* @divider: Divider fixed value.
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* @flags: Divider clock flags.
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* @features: CCU Divider private features.
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*/
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struct ccu_div {
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struct clk_hw hw;
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unsigned int id;
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unsigned int reg_ctl;
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struct regmap *sys_regs;
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spinlock_t lock;
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union {
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u32 mask;
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unsigned int divider;
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};
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unsigned long flags;
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unsigned long features;
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};
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#define to_ccu_div(_hw) container_of(_hw, struct ccu_div, hw)
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static inline struct clk_hw *ccu_div_get_clk_hw(struct ccu_div *div)
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{
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return div ? &div->hw : NULL;
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}
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struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *init);
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void ccu_div_hw_unregister(struct ccu_div *div);
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int ccu_div_reset_domain(struct ccu_div *div);
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#endif /* __CLK_BT1_CCU_DIV_H__ */
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