mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 11:30:54 +07:00
f15cbe6f1a
This follows the sparc changes a439fe51a1.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* include/asm-sh/cpu-sh3/gpio.h
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*
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* Copyright (C) 2007 Markus Brunner, Mark Jonas
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*
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* Addresses for the Pin Function Controller
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef _CPU_SH3_GPIO_H
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#define _CPU_SH3_GPIO_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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/* Control registers */
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#define PORT_PACR 0xA4050100UL
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#define PORT_PBCR 0xA4050102UL
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#define PORT_PCCR 0xA4050104UL
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#define PORT_PDCR 0xA4050106UL
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#define PORT_PECR 0xA4050108UL
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#define PORT_PFCR 0xA405010AUL
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#define PORT_PGCR 0xA405010CUL
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#define PORT_PHCR 0xA405010EUL
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#define PORT_PJCR 0xA4050110UL
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#define PORT_PKCR 0xA4050112UL
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#define PORT_PLCR 0xA4050114UL
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#define PORT_PMCR 0xA4050116UL
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#define PORT_PPCR 0xA4050118UL
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#define PORT_PRCR 0xA405011AUL
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#define PORT_PSCR 0xA405011CUL
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#define PORT_PTCR 0xA405011EUL
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#define PORT_PUCR 0xA4050120UL
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#define PORT_PVCR 0xA4050122UL
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/* Data registers */
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#define PORT_PADR 0xA4050140UL
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/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
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#define PORT_PBDR 0xA4050142UL
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#define PORT_PCDR 0xA4050144UL
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#define PORT_PDDR 0xA4050146UL
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#define PORT_PEDR 0xA4050148UL
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#define PORT_PFDR 0xA405014AUL
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#define PORT_PGDR 0xA405014CUL
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#define PORT_PHDR 0xA405014EUL
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#define PORT_PJDR 0xA4050150UL
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#define PORT_PKDR 0xA4050152UL
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#define PORT_PLDR 0xA4050154UL
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#define PORT_PMDR 0xA4050156UL
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#define PORT_PPDR 0xA4050158UL
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#define PORT_PRDR 0xA405015AUL
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#define PORT_PSDR 0xA405015CUL
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#define PORT_PTDR 0xA405015EUL
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#define PORT_PUDR 0xA4050160UL
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#define PORT_PVDR 0xA4050162UL
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/* Pin Select Registers */
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#define PORT_PSELA 0xA4050124UL
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#define PORT_PSELB 0xA4050126UL
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#define PORT_PSELC 0xA4050128UL
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#define PORT_PSELD 0xA405012AUL
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#endif
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#endif
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