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42181186ad
Mathieu Desnoyers pointed out a case that can cause issues with NMIs running on the debug stack: int3 -> interrupt -> NMI -> int3 Because the interrupt changes the stack, the NMI will not see that it preempted the debug stack. Looking deeper at this case, interrupts only happen when the int3 is from userspace or in an a location in the exception table (fixup). userspace -> int3 -> interurpt -> NMI -> int3 All other int3s that happen in the kernel should be processed without ever enabling interrupts, as the do_trap() call will panic the kernel if it is called to process any other location within the kernel. Adding a counter around the sections that enable interrupts while using the debug stack allows the NMI to also check that case. If the NMI sees that it either interrupted a task using the debug stack or the debug counter is non-zero, then it will have to change the IDT table to make the int3 not change stacks (which will corrupt the stack if it does). Note, I had to move the debug_usage functions out of processor.h and into debugreg.h because of the static inlined functions to inc and dec the debug_usage counter. __get_cpu_var() requires smp.h which includes processor.h, and would fail to build. Link: http://lkml.kernel.org/r/1323976535.23971.112.camel@gandalf.stny.rr.com Reported-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: H. Peter Anvin <hpa@linux.intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Paul Turner <pjt@google.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
129 lines
4.3 KiB
C
129 lines
4.3 KiB
C
#ifndef _ASM_X86_DEBUGREG_H
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#define _ASM_X86_DEBUGREG_H
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/* Indicate the register numbers for a number of the specific
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debug registers. Registers 0-3 contain the addresses we wish to trap on */
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#define DR_FIRSTADDR 0 /* u_debugreg[DR_FIRSTADDR] */
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#define DR_LASTADDR 3 /* u_debugreg[DR_LASTADDR] */
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#define DR_STATUS 6 /* u_debugreg[DR_STATUS] */
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#define DR_CONTROL 7 /* u_debugreg[DR_CONTROL] */
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/* Define a few things for the status register. We can use this to determine
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which debugging register was responsible for the trap. The other bits
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are either reserved or not of interest to us. */
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/* Define reserved bits in DR6 which are always set to 1 */
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#define DR6_RESERVED (0xFFFF0FF0)
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#define DR_TRAP0 (0x1) /* db0 */
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#define DR_TRAP1 (0x2) /* db1 */
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#define DR_TRAP2 (0x4) /* db2 */
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#define DR_TRAP3 (0x8) /* db3 */
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#define DR_TRAP_BITS (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)
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#define DR_STEP (0x4000) /* single-step */
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#define DR_SWITCH (0x8000) /* task switch */
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/* Now define a bunch of things for manipulating the control register.
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The top two bytes of the control register consist of 4 fields of 4
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bits - each field corresponds to one of the four debug registers,
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and indicates what types of access we trap on, and how large the data
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field is that we are looking at */
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#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
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#define DR_CONTROL_SIZE 4 /* 4 control bits per register */
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#define DR_RW_EXECUTE (0x0) /* Settings for the access types to trap on */
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#define DR_RW_WRITE (0x1)
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#define DR_RW_READ (0x3)
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#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
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#define DR_LEN_2 (0x4)
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#define DR_LEN_4 (0xC)
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#define DR_LEN_8 (0x8)
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/* The low byte to the control register determine which registers are
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enabled. There are 4 fields of two bits. One bit is "local", meaning
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that the processor will reset the bit after a task switch and the other
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is global meaning that we have to explicitly reset the bit. With linux,
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you can use either one, since we explicitly zero the register when we enter
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kernel mode. */
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#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit */
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#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit */
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#define DR_LOCAL_ENABLE (0x1) /* Local enable for reg 0 */
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#define DR_GLOBAL_ENABLE (0x2) /* Global enable for reg 0 */
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#define DR_ENABLE_SIZE 2 /* 2 enable bits per register */
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#define DR_LOCAL_ENABLE_MASK (0x55) /* Set local bits for all 4 regs */
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#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
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/* The second byte to the control register has a few special things.
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We can slow the instruction pipeline for instructions coming via the
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gdt or the ldt if we want to. I am not sure why this is an advantage */
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#ifdef __i386__
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#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
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#else
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#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
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#endif
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#define DR_LOCAL_SLOWDOWN (0x100) /* Local slow the pipeline */
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#define DR_GLOBAL_SLOWDOWN (0x200) /* Global slow the pipeline */
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/*
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* HW breakpoint additions
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*/
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#ifdef __KERNEL__
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DECLARE_PER_CPU(unsigned long, cpu_dr7);
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static inline void hw_breakpoint_disable(void)
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{
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/* Zero the control register for HW Breakpoint */
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set_debugreg(0UL, 7);
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/* Zero-out the individual HW breakpoint address registers */
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set_debugreg(0UL, 0);
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set_debugreg(0UL, 1);
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set_debugreg(0UL, 2);
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set_debugreg(0UL, 3);
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}
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static inline int hw_breakpoint_active(void)
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{
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return __this_cpu_read(cpu_dr7) & DR_GLOBAL_ENABLE_MASK;
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}
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extern void aout_dump_debugregs(struct user *dump);
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extern void hw_breakpoint_restore(void);
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#ifdef CONFIG_X86_64
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DECLARE_PER_CPU(int, debug_stack_usage);
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static inline void debug_stack_usage_inc(void)
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{
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__get_cpu_var(debug_stack_usage)++;
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}
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static inline void debug_stack_usage_dec(void)
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{
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__get_cpu_var(debug_stack_usage)--;
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}
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int is_debug_stack(unsigned long addr);
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void debug_stack_set_zero(void);
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void debug_stack_reset(void);
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#else /* !X86_64 */
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static inline int is_debug_stack(unsigned long addr) { return 0; }
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static inline void debug_stack_set_zero(void) { }
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static inline void debug_stack_reset(void) { }
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static inline void debug_stack_usage_inc(void) { }
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static inline void debug_stack_usage_dec(void) { }
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#endif /* X86_64 */
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_DEBUGREG_H */
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