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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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91305f2812
This patch is to support automatic configuration for ptp timer. If required ptp dts properties are not provided, driver could try to calculate a set of default configurations to initialize the ptp timer. This makes the driver work for many boards which don't have the required ptp dts properties in current kernel. Also the users could set dts properties by themselves according to their requirement. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
170 lines
6.2 KiB
C
170 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2010 OMICRON electronics GmbH
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* Copyright 2018 NXP
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*/
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#ifndef __PTP_QORIQ_H__
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#define __PTP_QORIQ_H__
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#include <linux/io.h>
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#include <linux/ptp_clock_kernel.h>
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/*
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* qoriq ptp registers
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*/
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struct ctrl_regs {
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u32 tmr_ctrl; /* Timer control register */
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u32 tmr_tevent; /* Timestamp event register */
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u32 tmr_temask; /* Timer event mask register */
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u32 tmr_pevent; /* Timestamp event register */
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u32 tmr_pemask; /* Timer event mask register */
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u32 tmr_stat; /* Timestamp status register */
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u32 tmr_cnt_h; /* Timer counter high register */
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u32 tmr_cnt_l; /* Timer counter low register */
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u32 tmr_add; /* Timer drift compensation addend register */
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u32 tmr_acc; /* Timer accumulator register */
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u32 tmr_prsc; /* Timer prescale */
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u8 res1[4];
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u32 tmroff_h; /* Timer offset high */
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u32 tmroff_l; /* Timer offset low */
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};
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struct alarm_regs {
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u32 tmr_alarm1_h; /* Timer alarm 1 high register */
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u32 tmr_alarm1_l; /* Timer alarm 1 high register */
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u32 tmr_alarm2_h; /* Timer alarm 2 high register */
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u32 tmr_alarm2_l; /* Timer alarm 2 high register */
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};
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struct fiper_regs {
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u32 tmr_fiper1; /* Timer fixed period interval */
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u32 tmr_fiper2; /* Timer fixed period interval */
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u32 tmr_fiper3; /* Timer fixed period interval */
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};
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struct etts_regs {
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u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
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u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
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u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
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u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
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};
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struct qoriq_ptp_registers {
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struct ctrl_regs __iomem *ctrl_regs;
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struct alarm_regs __iomem *alarm_regs;
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struct fiper_regs __iomem *fiper_regs;
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struct etts_regs __iomem *etts_regs;
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};
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/* Offset definitions for the four register groups */
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#define CTRL_REGS_OFFSET 0x0
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#define ALARM_REGS_OFFSET 0x40
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#define FIPER_REGS_OFFSET 0x80
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#define ETTS_REGS_OFFSET 0xa0
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#define FMAN_CTRL_REGS_OFFSET 0x80
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#define FMAN_ALARM_REGS_OFFSET 0xb8
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#define FMAN_FIPER_REGS_OFFSET 0xd0
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#define FMAN_ETTS_REGS_OFFSET 0xe0
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/* Bit definitions for the TMR_CTRL register */
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#define ALM1P (1<<31) /* Alarm1 output polarity */
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#define ALM2P (1<<30) /* Alarm2 output polarity */
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#define FIPERST (1<<28) /* FIPER start indication */
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#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
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#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
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#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
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#define TCLK_PERIOD_MASK (0x3ff)
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#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
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#define FRD (1<<14) /* FIPER Realignment Disable */
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#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
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#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
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#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
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#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
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#define COPH (1<<7) /* Generated clock output phase. */
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#define CIPH (1<<6) /* External oscillator input clock phase */
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#define TMSR (1<<5) /* Timer soft reset. */
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#define BYP (1<<3) /* Bypass drift compensated clock */
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#define TE (1<<2) /* 1588 timer enable. */
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#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
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#define CKSEL_MASK (0x3)
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/* Bit definitions for the TMR_TEVENT register */
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#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
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#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
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#define ALM2 (1<<17) /* Current time = alarm time register 2 */
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#define ALM1 (1<<16) /* Current time = alarm time register 1 */
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#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
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#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
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#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
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/* Bit definitions for the TMR_TEMASK register */
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#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
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#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
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#define ALM2EN (1<<17) /* Timer ALM2 event enable */
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#define ALM1EN (1<<16) /* Timer ALM1 event enable */
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#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
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#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
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/* Bit definitions for the TMR_PEVENT register */
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#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
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#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
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#define RXP (1<<0) /* PTP frame has been received */
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/* Bit definitions for the TMR_PEMASK register */
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#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
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#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
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#define RXPEN (1<<0) /* Receive PTP packet event enable */
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/* Bit definitions for the TMR_STAT register */
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#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
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#define STAT_VEC_MASK (0x3f)
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/* Bit definitions for the TMR_PRSC register */
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#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
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#define PRSC_OCK_MASK (0xffff)
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#define DRIVER "ptp_qoriq"
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#define N_EXT_TS 2
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#define DEFAULT_CKSEL 1
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#define DEFAULT_TMR_PRSC 2
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#define DEFAULT_FIPER1_PERIOD 1000000000
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#define DEFAULT_FIPER2_PERIOD 100000
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struct qoriq_ptp {
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void __iomem *base;
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struct qoriq_ptp_registers regs;
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spinlock_t lock; /* protects regs */
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struct ptp_clock *clock;
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struct ptp_clock_info caps;
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struct resource *rsrc;
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int irq;
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int phc_index;
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u64 alarm_interval; /* for periodic alarm */
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u64 alarm_value;
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u32 tclk_period; /* nanoseconds */
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u32 tmr_prsc;
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u32 tmr_add;
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u32 cksel;
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u32 tmr_fiper1;
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u32 tmr_fiper2;
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};
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static inline u32 qoriq_read(unsigned __iomem *addr)
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{
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u32 val;
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val = ioread32be(addr);
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return val;
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}
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static inline void qoriq_write(unsigned __iomem *addr, u32 val)
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{
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iowrite32be(val, addr);
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}
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#endif
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