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22b6c9e8fe
This patch adds support for advanced features supported by the Noise-Aware PLL of Maxwell. Glitchless switch allows the PL field to be updated without disabling the PLL first if the SYNC_MODE bit of the CFG register is set. More significantly, DFS allows the PLL to monitor the actual input voltage and to dynamically lower the output frequency accordingly. This allows the clock to be more tolerant of lower voltages. These improvements are only supported for Tegra speedos >= 1. Also add the voltage table that is suitable for GM20B's NAPLL. This change needs to be done atomically for the right voltages to be used by the clock driver. v2. Fix build on non-Tegra platforms Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> |
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