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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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227e3958a7
read_boot_clock64() is deleted, and replaced with read_persistent_wall_and_boot_offset(). The default implementation of read_persistent_wall_and_boot_offset() provides a better fallback than the current stubs for read_boot_clock64() that arm has with no users, so remove the old code. Signed-off-by: Pavel Tatashin <pasha.tatashin@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: steven.sistare@oracle.com Cc: daniel.m.jordan@oracle.com Cc: linux@armlinux.org.uk Cc: schwidefsky@de.ibm.com Cc: heiko.carstens@de.ibm.com Cc: john.stultz@linaro.org Cc: sboyd@codeaurora.org Cc: hpa@zytor.com Cc: douly.fnst@cn.fujitsu.com Cc: peterz@infradead.org Cc: prarit@redhat.com Cc: feng.tang@intel.com Cc: pmladek@suse.com Cc: gnomes@lxorguk.ukuu.org.uk Cc: linux-s390@vger.kernel.org Cc: boris.ostrovsky@oracle.com Cc: jgross@suse.com Cc: pbonzini@redhat.com Link: https://lkml.kernel.org/r/20180719205545.16512-19-pasha.tatashin@oracle.com
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/*
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* OMAP 32ksynctimer/counter_32k-related code
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*
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* Copyright (C) 2009 Texas Instruments
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* Copyright (C) 2010 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clocksource.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/time.h>
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#include <plat/counter-32k.h>
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/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
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#define OMAP2_32KSYNCNT_REV_OFF 0x0
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#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
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#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
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#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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static void __iomem *sync32k_cnt_reg;
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static u64 notrace omap_32k_read_sched_clock(void)
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{
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return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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}
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/**
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* omap_read_persistent_clock64 - Return time from a persistent clock.
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*
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* Reads the time from a source which isn't disabled during PM, the
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* 32k sync timer. Convert the cycles elapsed since last read into
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* nsecs and adds to a monotonically increasing timespec64.
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*/
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static struct timespec64 persistent_ts;
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static cycles_t cycles;
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static unsigned int persistent_mult, persistent_shift;
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static void omap_read_persistent_clock64(struct timespec64 *ts)
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{
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unsigned long long nsecs;
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cycles_t last_cycles;
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last_cycles = cycles;
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cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
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nsecs = clocksource_cyc2ns(cycles - last_cycles,
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persistent_mult, persistent_shift);
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timespec64_add_ns(&persistent_ts, nsecs);
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*ts = persistent_ts;
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}
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/**
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* omap_init_clocksource_32k - setup and register counter 32k as a
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* kernel clocksource
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* @pbase: base addr of counter_32k module
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* @size: size of counter_32k to map
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*
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* Returns 0 upon success or negative error code upon failure.
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*
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*/
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int __init omap_init_clocksource_32k(void __iomem *vbase)
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{
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int ret;
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/*
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* 32k sync Counter IP register offsets vary between the
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* highlander version and the legacy ones.
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* The 'SCHEME' bits(30-31) of the revision register is used
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* to identify the version.
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*/
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if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
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OMAP2_32KSYNCNT_REV_SCHEME)
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
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else
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sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
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/*
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* 120000 rough estimate from the calculations in
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* __clocksource_update_freq_scale.
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*/
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clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
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32768, NSEC_PER_SEC, 120000);
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ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
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250, 32, clocksource_mmio_readl_up);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return ret;
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}
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sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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register_persistent_clock(omap_read_persistent_clock64);
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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return 0;
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}
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