mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1dfb26df15
[ Upstream commit 43262178c043032e7c42d00de44c818ba05f9967 ] Don't clear the timer 1 configuration bits when clearing the interrupt flag and counter overflow. As Michael reported, "This results in no timer interrupts being delivered after the first. Initialization then hangs in calibrate_delay as the jiffies counter is not updated." On mvme16x, enable the timer after requesting the irq, consistent with mvme147. Cc: Michael Pavone <pavone@retrodev.com> Fixes:7529b90d05
("m68k: mvme147: Handle timer counter overflow") Fixes:19999a8b87
("m68k: mvme16x: Handle timer counter overflow") Reported-and-tested-by: Michael Pavone <pavone@retrodev.com> Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Link: https://lore.kernel.org/r/4fdaa113db089b8fb607f7dd818479f8cdcc4547.1617089871.git.fthain@telegraphics.com.au Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
191 lines
4.5 KiB
C
191 lines
4.5 KiB
C
/*
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* arch/m68k/mvme147/config.c
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*
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* Copyright (C) 1996 Dave Frascone [chaos@mindspring.com]
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* Cloned from Richard Hirst [richard@sleepie.demon.co.uk]
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*
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* Based on:
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*
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* Copyright (C) 1993 Hamish Macdonald
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file README.legal in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/tty.h>
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#include <linux/clocksource.h>
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#include <linux/console.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <linux/major.h>
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#include <linux/genhd.h>
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#include <linux/rtc.h>
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#include <linux/interrupt.h>
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#include <asm/bootinfo.h>
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#include <asm/bootinfo-vme.h>
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#include <asm/byteorder.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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#include <asm/mvme147hw.h>
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static void mvme147_get_model(char *model);
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extern void mvme147_sched_init(irq_handler_t handler);
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extern int mvme147_hwclk (int, struct rtc_time *);
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extern void mvme147_reset (void);
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static int bcd2int (unsigned char b);
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int __init mvme147_parse_bootinfo(const struct bi_record *bi)
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{
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uint16_t tag = be16_to_cpu(bi->tag);
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if (tag == BI_VME_TYPE || tag == BI_VME_BRDINFO)
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return 0;
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else
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return 1;
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}
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void mvme147_reset(void)
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{
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pr_info("\r\n\nCalled mvme147_reset\r\n");
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m147_pcc->watchdog = 0x0a; /* Clear timer */
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m147_pcc->watchdog = 0xa5; /* Enable watchdog - 100ms to reset */
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while (1)
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;
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}
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static void mvme147_get_model(char *model)
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{
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sprintf(model, "Motorola MVME147");
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}
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/*
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* This function is called during kernel startup to initialize
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* the mvme147 IRQ handling routines.
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*/
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void __init mvme147_init_IRQ(void)
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{
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m68k_setup_user_interrupt(VEC_USER, 192);
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}
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void __init config_mvme147(void)
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{
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mach_max_dma_address = 0x01000000;
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mach_sched_init = mvme147_sched_init;
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mach_init_IRQ = mvme147_init_IRQ;
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mach_hwclk = mvme147_hwclk;
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mach_reset = mvme147_reset;
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mach_get_model = mvme147_get_model;
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/* Board type is only set by newer versions of vmelilo/tftplilo */
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if (!vme_brdtype)
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vme_brdtype = VME_TYPE_MVME147;
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}
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static u64 mvme147_read_clk(struct clocksource *cs);
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static struct clocksource mvme147_clk = {
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.name = "pcc",
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.rating = 250,
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.read = mvme147_read_clk,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static u32 clk_total;
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#define PCC_TIMER_CLOCK_FREQ 160000
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#define PCC_TIMER_CYCLES (PCC_TIMER_CLOCK_FREQ / HZ)
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#define PCC_TIMER_PRELOAD (0x10000 - PCC_TIMER_CYCLES)
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/* Using pcc tick timer 1 */
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static irqreturn_t mvme147_timer_int (int irq, void *dev_id)
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{
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irq_handler_t timer_routine = dev_id;
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unsigned long flags;
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local_irq_save(flags);
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m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
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PCC_TIMER_TIC_EN;
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m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
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PCC_LEVEL_TIMER1;
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clk_total += PCC_TIMER_CYCLES;
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timer_routine(0, NULL);
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local_irq_restore(flags);
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return IRQ_HANDLED;
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}
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void mvme147_sched_init (irq_handler_t timer_routine)
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{
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if (request_irq(PCC_IRQ_TIMER1, mvme147_timer_int, IRQF_TIMER,
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"timer 1", timer_routine))
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pr_err("Couldn't register timer interrupt\n");
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/* Init the clock with a value */
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/* The clock counter increments until 0xFFFF then reloads */
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m147_pcc->t1_preload = PCC_TIMER_PRELOAD;
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m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
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PCC_TIMER_TIC_EN;
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m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
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PCC_LEVEL_TIMER1;
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clocksource_register_hz(&mvme147_clk, PCC_TIMER_CLOCK_FREQ);
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}
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static u64 mvme147_read_clk(struct clocksource *cs)
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{
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unsigned long flags;
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u8 overflow, tmp;
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u16 count;
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u32 ticks;
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local_irq_save(flags);
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tmp = m147_pcc->t1_cntrl >> 4;
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count = m147_pcc->t1_count;
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overflow = m147_pcc->t1_cntrl >> 4;
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if (overflow != tmp)
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count = m147_pcc->t1_count;
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count -= PCC_TIMER_PRELOAD;
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ticks = count + overflow * PCC_TIMER_CYCLES;
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ticks += clk_total;
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local_irq_restore(flags);
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return ticks;
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}
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static int bcd2int (unsigned char b)
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{
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return ((b>>4)*10 + (b&15));
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}
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int mvme147_hwclk(int op, struct rtc_time *t)
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{
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#warning check me!
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if (!op) {
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m147_rtc->ctrl = RTC_READ;
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t->tm_year = bcd2int (m147_rtc->bcd_year);
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t->tm_mon = bcd2int(m147_rtc->bcd_mth) - 1;
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t->tm_mday = bcd2int (m147_rtc->bcd_dom);
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t->tm_hour = bcd2int (m147_rtc->bcd_hr);
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t->tm_min = bcd2int (m147_rtc->bcd_min);
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t->tm_sec = bcd2int (m147_rtc->bcd_sec);
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m147_rtc->ctrl = 0;
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if (t->tm_year < 70)
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t->tm_year += 100;
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}
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return 0;
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}
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