Sean Christopherson 567926cca9 KVM: nVMX: Fix consistency check on injected exception error code ... Current versions of Intel's SDM incorrectly state that "bits 31:15 of the VM-Entry exception error-code field" must be zero. In reality, bits 31:16 must be zero, i.e. error codes are 16-bit values. The bogus error code check manifests as an unexpected VM-Entry failure due to an invalid code field (error number 7) in L1, e.g. when injecting a #GP with error_code=0x9f00. Nadav previously reported the bug[*], both to KVM and Intel, and fixed the associated kvm-unit-test. [*] https://patchwork.kernel.org/patch/11124749/ Reported-by: Nadav Amit <namit@vmware.com> Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Reviewed-by: Jim Mattson <jmattson@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>		2019-10-03 12:32:44 +02:00
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capabilities.h	KVM: x86: Add support for user wait instructions	2019-09-24 14:34:20 +02:00
evmcs.c
evmcs.h	KVM/Hyper-V/VMX: Add direct tlb flush support	2019-09-24 13:37:14 +02:00
nested.c	KVM: nVMX: Fix consistency check on injected exception error code	2019-10-03 12:32:44 +02:00
nested.h
ops.h	KVM: VMX: Add error handling to VMREAD helper	2019-09-25 15:30:09 +02:00
pmu_intel.c	kvm: vmx: Limit guest PMCs to those supported on the host	2019-10-01 15:15:06 +02:00
vmcs12.c
vmcs12.h
vmcs_shadow_fields.h
vmcs.h
vmenter.S	KVM: VMX: Fix and tweak the comments for VM-Enter	2019-08-22 10:09:27 +02:00
vmx.c	KVM: VMX: Set VMENTER_L1D_FLUSH_NOT_REQUIRED if !X86_BUG_L1TF	2019-09-27 18:04:18 +02:00
vmx.h	KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL	2019-09-24 14:34:36 +02:00