mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 16:36:55 +07:00
ce61b49096
The JZ4740 setup code is not a clock provider, and just needs to call
of_clk_init().
Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>.
Fixes: f932449c11 ("MIPS: ingenic: Drop obsolete code, merge the rest in setup.c")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
163 lines
3.1 KiB
C
163 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* Copyright (C) 2011, Maarten ter Huurne <maarten@treewalker.org>
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* JZ4740 setup code
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*/
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#include <linux/clocksource.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/libfdt.h>
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#include <linux/of_clk.h>
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#include <linux/of_fdt.h>
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <asm/bootinfo.h>
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#include <asm/fw/fw.h>
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#include <asm/prom.h>
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#include <asm/reboot.h>
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#define JZ4740_EMC_BASE_ADDR 0x13010000
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#define JZ4740_EMC_SDRAM_CTRL 0x80
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static void __init jz4740_detect_mem(void)
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{
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void __iomem *jz_emc_base;
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u32 ctrl, bus, bank, rows, cols;
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phys_addr_t size;
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jz_emc_base = ioremap(JZ4740_EMC_BASE_ADDR, 0x100);
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ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL);
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bus = 2 - ((ctrl >> 31) & 1);
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bank = 1 + ((ctrl >> 19) & 1);
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cols = 8 + ((ctrl >> 26) & 7);
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rows = 11 + ((ctrl >> 20) & 3);
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printk(KERN_DEBUG
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"SDRAM preconfigured: bus:%u bank:%u rows:%u cols:%u\n",
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bus, bank, rows, cols);
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iounmap(jz_emc_base);
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size = 1 << (bus + bank + cols + rows);
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add_memory_region(0, size, BOOT_MEM_RAM);
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}
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static unsigned long __init get_board_mach_type(const void *fdt)
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{
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1830"))
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return MACH_INGENIC_X1830;
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,x1000"))
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return MACH_INGENIC_X1000;
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4780"))
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return MACH_INGENIC_JZ4780;
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if (!fdt_node_check_compatible(fdt, 0, "ingenic,jz4770"))
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return MACH_INGENIC_JZ4770;
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return MACH_INGENIC_JZ4740;
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}
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void __init plat_mem_setup(void)
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{
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int offset;
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void *dtb;
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if (__dtb_start != __dtb_end)
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dtb = __dtb_start;
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else
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dtb = (void *)fw_passed_dtb;
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__dt_setup_arch(dtb);
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offset = fdt_path_offset(dtb, "/memory");
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if (offset < 0)
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jz4740_detect_mem();
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mips_machtype = get_board_mach_type(dtb);
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}
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void __init device_tree_init(void)
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{
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if (!initial_boot_params)
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return;
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unflatten_and_copy_device_tree();
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}
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const char *get_system_type(void)
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{
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switch (mips_machtype) {
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case MACH_INGENIC_X1830:
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return "X1830";
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case MACH_INGENIC_X1000:
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return "X1000";
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case MACH_INGENIC_JZ4780:
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return "JZ4780";
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case MACH_INGENIC_JZ4770:
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return "JZ4770";
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default:
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return "JZ4740";
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}
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}
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void __init arch_init_irq(void)
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{
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irqchip_init();
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}
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void __init plat_time_init(void)
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{
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of_clk_init(NULL);
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timer_probe();
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}
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void __init prom_init(void)
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{
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fw_init_cmdline();
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}
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void __init prom_free_prom_memory(void)
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{
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}
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static void jz4740_wait_instr(void)
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{
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__asm__(".set push;\n"
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".set mips3;\n"
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"wait;\n"
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".set pop;\n"
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);
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}
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static void jz4740_halt(void)
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{
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for (;;)
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jz4740_wait_instr();
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}
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static int __maybe_unused jz4740_pm_enter(suspend_state_t state)
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{
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jz4740_wait_instr();
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return 0;
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}
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static const struct platform_suspend_ops jz4740_pm_ops __maybe_unused = {
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.valid = suspend_valid_only_mem,
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.enter = jz4740_pm_enter,
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};
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static int __init jz4740_pm_init(void)
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{
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if (IS_ENABLED(CONFIG_PM_SLEEP))
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suspend_set_ops(&jz4740_pm_ops);
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_machine_halt = jz4740_halt;
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return 0;
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}
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late_initcall(jz4740_pm_init);
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