Paulo Zanoni 221ab43e8a drm/i915: don't read or write GEN6_PMIIR on Gen 5 ... The register doesn't exist on Gen 5. v2: Simplify checks since pm_iir is always 0 on Gen 5 (Chris) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2013-07-19 18:05:14 +02:00
..
drm	drm/i915: don't read or write GEN6_PMIIR on Gen 5	2013-07-19 18:05:14 +02:00
host1x	gpu: host1x: Rework CPU syncpoint increment	2013-06-22 12:43:55 +02:00
vga	fbcon: fix locking harder	2013-02-08 12:02:43 +10:00
Makefile	gpu: host1x: Add host1x driver	2013-04-22 12:32:40 +02:00