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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f52c380a48
1) Use standard i915 GEM object sequence to access the shadow batch buffer. 2) Manage i915 vma life cycle to solve one FIXME. v2: - Refine code structure. - Refine the usage of GEM APIs. - Add the missing lock/unlock in release_shadow_batch_buffer. Test on my SKL NuC. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
161 lines
4.7 KiB
C
161 lines
4.7 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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* Contributors:
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* Ping Gao <ping.a.gao@intel.com>
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* Tina Zhang <tina.zhang@intel.com>
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* Chanbin Du <changbin.du@intel.com>
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* Min He <min.he@intel.com>
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* Bing Niu <bing.niu@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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*
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*/
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#ifndef _GVT_SCHEDULER_H_
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#define _GVT_SCHEDULER_H_
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struct intel_gvt_workload_scheduler {
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struct intel_vgpu *current_vgpu;
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struct intel_vgpu *next_vgpu;
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struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
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bool need_reschedule;
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spinlock_t mmio_context_lock;
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/* can be null when owner is host */
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struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
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wait_queue_head_t workload_complete_wq;
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struct task_struct *thread[I915_NUM_ENGINES];
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wait_queue_head_t waitq[I915_NUM_ENGINES];
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void *sched_data;
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struct intel_gvt_sched_policy_ops *sched_ops;
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};
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#define INDIRECT_CTX_ADDR_MASK 0xffffffc0
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#define INDIRECT_CTX_SIZE_MASK 0x3f
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struct shadow_indirect_ctx {
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struct drm_i915_gem_object *obj;
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unsigned long guest_gma;
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unsigned long shadow_gma;
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void *shadow_va;
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uint32_t size;
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};
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#define PER_CTX_ADDR_MASK 0xfffff000
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struct shadow_per_ctx {
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unsigned long guest_gma;
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unsigned long shadow_gma;
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unsigned valid;
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};
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struct intel_shadow_wa_ctx {
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struct shadow_indirect_ctx indirect_ctx;
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struct shadow_per_ctx per_ctx;
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};
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struct intel_vgpu_workload {
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struct intel_vgpu *vgpu;
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int ring_id;
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struct drm_i915_gem_request *req;
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/* if this workload has been dispatched to i915? */
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bool dispatched;
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bool shadowed;
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int status;
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struct intel_vgpu_mm *shadow_mm;
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/* different submission model may need different handler */
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int (*prepare)(struct intel_vgpu_workload *);
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int (*complete)(struct intel_vgpu_workload *);
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struct list_head list;
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DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
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void *shadow_ring_buffer_va;
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/* execlist context information */
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struct execlist_ctx_descriptor_format ctx_desc;
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struct execlist_ring_context *ring_context;
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unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
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bool restore_inhibit;
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struct intel_vgpu_elsp_dwords elsp_dwords;
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bool emulate_schedule_in;
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atomic_t shadow_ctx_active;
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wait_queue_head_t shadow_ctx_status_wq;
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u64 ring_context_gpa;
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/* shadow batch buffer */
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struct list_head shadow_bb;
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struct intel_shadow_wa_ctx wa_ctx;
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};
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struct intel_vgpu_shadow_bb {
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struct list_head list;
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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void *va;
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u32 *bb_start_cmd_va;
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unsigned int clflush;
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bool accessing;
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};
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#define workload_q_head(vgpu, ring_id) \
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(&(vgpu->submission.workload_q_head[ring_id]))
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#define queue_workload(workload) do { \
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list_add_tail(&workload->list, \
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workload_q_head(workload->vgpu, workload->ring_id)); \
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wake_up(&workload->vgpu->gvt-> \
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scheduler.waitq[workload->ring_id]); \
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} while (0)
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int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
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void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
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void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu);
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int intel_vgpu_setup_submission(struct intel_vgpu *vgpu);
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void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
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unsigned long engine_mask);
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void intel_vgpu_clean_submission(struct intel_vgpu *vgpu);
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int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
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unsigned int interface);
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extern const struct intel_vgpu_submission_ops
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intel_vgpu_execlist_submission_ops;
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struct intel_vgpu_workload *
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intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
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struct execlist_ctx_descriptor_format *desc);
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void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload);
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#endif
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