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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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aaf6c75c04
Silicon Linux CAT 874 board has 2GB DDR memory. Update the dma-ranges mapping for pciec0 node. Also declare pcie bus clock, since it is generated on the CAT874 main board. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
107 lines
2.0 KiB
Plaintext
107 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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/dts-v1/;
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#include "r8a774c0.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Silicon Linux RZ/G2E 96board platform (CAT874)";
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compatible = "si-linux,cat874", "renesas,r8a774c0";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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vcc_sdhi0: regulator-vcc-sdhi0 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vccq_sdhi0: regulator-vccq-sdhi0 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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};
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&extal_clk {
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clock-frequency = <48000000>;
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};
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&pcie_bus_clk {
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clock-frequency = <100000000>;
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};
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&pciec0 {
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/* Map all possible DDR as inbound ranges */
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
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};
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&pfc {
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scif2_pins: scif2 {
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groups = "scif2_data_a";
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function = "scif2";
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};
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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sdhi0_pins_uhs: sd0_uhs {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <1800>;
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};
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};
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&scif2 {
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-1 = <&sdhi0_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi0>;
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vqmmc-supply = <&vccq_sdhi0>;
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cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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status = "okay";
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};
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