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2167ceabf3
AMD Fam17h processors introduce support for the CLZERO instruction. It zeroes out the 64 byte cache line specified in RAX. Add the bit here to allow /proc/cpuinfo to list the feature. Boris: we're adding this as a separate ->x86_capability leaf because CPUID_80000008_EBX is going to contain more feature bits and it will fill out with time. Signed-off-by: Wan Zongshun <Vincent.Wan@amd.com> Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> [ Wrap code in patch form, fix comments. ] Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Huang Rui <ray.huang@amd.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1446207099-24948-4-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org> |
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| common.c | ||
| cpu.h | ||
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| intel_cacheinfo.c | ||
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| intel.c | ||
| Makefile | ||
| match.c | ||
| mkcapflags.sh | ||
| mshyperv.c | ||
| perf_event_amd_ibs.c | ||
| perf_event_amd_iommu.c | ||
| perf_event_amd_iommu.h | ||
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| perf_event_intel_bts.c | ||
| perf_event_intel_cqm.c | ||
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| perf_event_intel_uncore_nhmex.c | ||
| perf_event_intel_uncore_snb.c | ||
| perf_event_intel_uncore_snbep.c | ||
| perf_event_intel_uncore.c | ||
| perf_event_intel_uncore.h | ||
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| perf_event.c | ||
| perf_event.h | ||
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| powerflags.c | ||
| proc.c | ||
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| topology.c | ||
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