mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 12:36:59 +07:00
c029b5deb0
MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. Availability of the MOVDIR64B instruction is indicated by the presence of the CPUID feature flag MOVDIR64B (CPUID.0x07.0x0:ECX[bit 28]). This patch exposes the movdir64b feature to the guest. The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Liu Jingqi <jingqi.liu@intel.com> Cc: Xu Tao <tao3.xu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
971 lines
25 KiB
C
971 lines
25 KiB
C
/*
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* Kernel-based Virtual Machine driver for Linux
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* cpuid support routines
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*
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* derived from arch/x86/kvm/x86.c
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*
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* Copyright 2011 Red Hat, Inc. and/or its affiliates.
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* Copyright IBM Corporation, 2008
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include <linux/kvm_host.h>
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#include <linux/export.h>
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#include <linux/vmalloc.h>
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#include <linux/uaccess.h>
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#include <linux/sched/stat.h>
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#include <asm/processor.h>
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#include <asm/user.h>
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#include <asm/fpu/xstate.h>
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#include "cpuid.h"
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#include "lapic.h"
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#include "mmu.h"
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#include "trace.h"
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#include "pmu.h"
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static u32 xstate_required_size(u64 xstate_bv, bool compacted)
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{
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int feature_bit = 0;
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u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
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xstate_bv &= XFEATURE_MASK_EXTEND;
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while (xstate_bv) {
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if (xstate_bv & 0x1) {
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u32 eax, ebx, ecx, edx, offset;
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cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
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offset = compacted ? ret : ebx;
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ret = max(ret, offset + eax);
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}
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xstate_bv >>= 1;
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feature_bit++;
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}
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return ret;
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}
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bool kvm_mpx_supported(void)
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{
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return ((host_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
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&& kvm_x86_ops->mpx_supported());
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}
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EXPORT_SYMBOL_GPL(kvm_mpx_supported);
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u64 kvm_supported_xcr0(void)
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{
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u64 xcr0 = KVM_SUPPORTED_XCR0 & host_xcr0;
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if (!kvm_mpx_supported())
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xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
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return xcr0;
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}
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#define F(x) bit(X86_FEATURE_##x)
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int kvm_update_cpuid(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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struct kvm_lapic *apic = vcpu->arch.apic;
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best = kvm_find_cpuid_entry(vcpu, 1, 0);
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if (!best)
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return 0;
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/* Update OSXSAVE bit */
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if (boot_cpu_has(X86_FEATURE_XSAVE) && best->function == 0x1) {
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best->ecx &= ~F(OSXSAVE);
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if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
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best->ecx |= F(OSXSAVE);
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}
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best->edx &= ~F(APIC);
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if (vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)
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best->edx |= F(APIC);
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if (apic) {
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if (best->ecx & F(TSC_DEADLINE_TIMER))
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apic->lapic_timer.timer_mode_mask = 3 << 17;
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else
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apic->lapic_timer.timer_mode_mask = 1 << 17;
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}
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best = kvm_find_cpuid_entry(vcpu, 7, 0);
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if (best) {
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/* Update OSPKE bit */
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if (boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) {
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best->ecx &= ~F(OSPKE);
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if (kvm_read_cr4_bits(vcpu, X86_CR4_PKE))
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best->ecx |= F(OSPKE);
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}
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}
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best = kvm_find_cpuid_entry(vcpu, 0xD, 0);
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if (!best) {
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vcpu->arch.guest_supported_xcr0 = 0;
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vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
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} else {
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vcpu->arch.guest_supported_xcr0 =
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(best->eax | ((u64)best->edx << 32)) &
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kvm_supported_xcr0();
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vcpu->arch.guest_xstate_size = best->ebx =
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xstate_required_size(vcpu->arch.xcr0, false);
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}
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best = kvm_find_cpuid_entry(vcpu, 0xD, 1);
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if (best && (best->eax & (F(XSAVES) | F(XSAVEC))))
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best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
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/*
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* The existing code assumes virtual address is 48-bit or 57-bit in the
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* canonical address checks; exit if it is ever changed.
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*/
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best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
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if (best) {
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int vaddr_bits = (best->eax & 0xff00) >> 8;
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if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
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return -EINVAL;
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}
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best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0);
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if (kvm_hlt_in_guest(vcpu->kvm) && best &&
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(best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
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best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
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/* Update physical-address width */
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vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
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kvm_mmu_reset_context(vcpu);
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kvm_pmu_refresh(vcpu);
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return 0;
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}
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static int is_efer_nx(void)
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{
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unsigned long long efer = 0;
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rdmsrl_safe(MSR_EFER, &efer);
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return efer & EFER_NX;
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}
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static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
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{
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int i;
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struct kvm_cpuid_entry2 *e, *entry;
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entry = NULL;
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for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
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e = &vcpu->arch.cpuid_entries[i];
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if (e->function == 0x80000001) {
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entry = e;
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break;
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}
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}
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if (entry && (entry->edx & F(NX)) && !is_efer_nx()) {
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entry->edx &= ~F(NX);
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printk(KERN_INFO "kvm: guest NX capability removed\n");
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}
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}
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int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
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if (!best || best->eax < 0x80000008)
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goto not_found;
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best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
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if (best)
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return best->eax & 0xff;
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not_found:
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return 36;
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}
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EXPORT_SYMBOL_GPL(cpuid_query_maxphyaddr);
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/* when an old userspace process fills a new kernel module */
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int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
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struct kvm_cpuid *cpuid,
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struct kvm_cpuid_entry __user *entries)
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{
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int r, i;
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struct kvm_cpuid_entry *cpuid_entries = NULL;
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r = -E2BIG;
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if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
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goto out;
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r = -ENOMEM;
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if (cpuid->nent) {
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cpuid_entries =
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vmalloc(array_size(sizeof(struct kvm_cpuid_entry),
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cpuid->nent));
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if (!cpuid_entries)
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goto out;
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r = -EFAULT;
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if (copy_from_user(cpuid_entries, entries,
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cpuid->nent * sizeof(struct kvm_cpuid_entry)))
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goto out;
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}
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for (i = 0; i < cpuid->nent; i++) {
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vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
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vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
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vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
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vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
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vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
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vcpu->arch.cpuid_entries[i].index = 0;
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vcpu->arch.cpuid_entries[i].flags = 0;
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vcpu->arch.cpuid_entries[i].padding[0] = 0;
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vcpu->arch.cpuid_entries[i].padding[1] = 0;
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vcpu->arch.cpuid_entries[i].padding[2] = 0;
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}
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vcpu->arch.cpuid_nent = cpuid->nent;
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cpuid_fix_nx_cap(vcpu);
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kvm_apic_set_version(vcpu);
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kvm_x86_ops->cpuid_update(vcpu);
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r = kvm_update_cpuid(vcpu);
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out:
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vfree(cpuid_entries);
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return r;
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}
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int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
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struct kvm_cpuid2 *cpuid,
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struct kvm_cpuid_entry2 __user *entries)
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{
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int r;
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r = -E2BIG;
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if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
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goto out;
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r = -EFAULT;
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if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
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cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
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goto out;
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vcpu->arch.cpuid_nent = cpuid->nent;
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kvm_apic_set_version(vcpu);
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kvm_x86_ops->cpuid_update(vcpu);
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r = kvm_update_cpuid(vcpu);
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out:
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return r;
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}
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int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
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struct kvm_cpuid2 *cpuid,
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struct kvm_cpuid_entry2 __user *entries)
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{
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int r;
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r = -E2BIG;
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if (cpuid->nent < vcpu->arch.cpuid_nent)
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goto out;
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r = -EFAULT;
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if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
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vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
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goto out;
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return 0;
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out:
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cpuid->nent = vcpu->arch.cpuid_nent;
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return r;
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}
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static void cpuid_mask(u32 *word, int wordnum)
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{
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*word &= boot_cpu_data.x86_capability[wordnum];
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}
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static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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u32 index)
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{
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entry->function = function;
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entry->index = index;
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cpuid_count(entry->function, entry->index,
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&entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
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entry->flags = 0;
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}
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static int __do_cpuid_ent_emulated(struct kvm_cpuid_entry2 *entry,
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u32 func, u32 index, int *nent, int maxnent)
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{
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switch (func) {
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case 0:
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entry->eax = 7;
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++*nent;
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break;
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case 1:
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entry->ecx = F(MOVBE);
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++*nent;
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break;
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case 7:
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entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
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if (index == 0)
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entry->ecx = F(RDPID);
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++*nent;
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default:
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break;
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}
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entry->function = func;
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entry->index = index;
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return 0;
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}
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static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
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u32 index, int *nent, int maxnent)
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{
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int r;
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unsigned f_nx = is_efer_nx() ? F(NX) : 0;
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#ifdef CONFIG_X86_64
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unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
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? F(GBPAGES) : 0;
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unsigned f_lm = F(LM);
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#else
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unsigned f_gbpages = 0;
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unsigned f_lm = 0;
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#endif
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unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
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unsigned f_invpcid = kvm_x86_ops->invpcid_supported() ? F(INVPCID) : 0;
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unsigned f_mpx = kvm_mpx_supported() ? F(MPX) : 0;
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unsigned f_xsaves = kvm_x86_ops->xsaves_supported() ? F(XSAVES) : 0;
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unsigned f_umip = kvm_x86_ops->umip_emulated() ? F(UMIP) : 0;
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unsigned f_intel_pt = kvm_x86_ops->pt_supported() ? F(INTEL_PT) : 0;
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/* cpuid 1.edx */
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const u32 kvm_cpuid_1_edx_x86_features =
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F(FPU) | F(VME) | F(DE) | F(PSE) |
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F(TSC) | F(MSR) | F(PAE) | F(MCE) |
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F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
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F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
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F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
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0 /* Reserved, DS, ACPI */ | F(MMX) |
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F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
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0 /* HTT, TM, Reserved, PBE */;
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/* cpuid 0x80000001.edx */
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const u32 kvm_cpuid_8000_0001_edx_x86_features =
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F(FPU) | F(VME) | F(DE) | F(PSE) |
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F(TSC) | F(MSR) | F(PAE) | F(MCE) |
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F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
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F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
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F(PAT) | F(PSE36) | 0 /* Reserved */ |
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f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
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F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
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0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
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/* cpuid 1.ecx */
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const u32 kvm_cpuid_1_ecx_x86_features =
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/* NOTE: MONITOR (and MWAIT) are emulated as NOP,
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* but *not* advertised to guests via CPUID ! */
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F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
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0 /* DS-CPL, VMX, SMX, EST */ |
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0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
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F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
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F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
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F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
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0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
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F(F16C) | F(RDRAND);
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/* cpuid 0x80000001.ecx */
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const u32 kvm_cpuid_8000_0001_ecx_x86_features =
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F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
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F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
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F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
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0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
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F(TOPOEXT) | F(PERFCTR_CORE);
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/* cpuid 0x80000008.ebx */
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const u32 kvm_cpuid_8000_0008_ebx_x86_features =
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F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
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F(AMD_SSB_NO) | F(AMD_STIBP);
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/* cpuid 0xC0000001.edx */
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const u32 kvm_cpuid_C000_0001_edx_x86_features =
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F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
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F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
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F(PMM) | F(PMM_EN);
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|
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/* cpuid 7.0.ebx */
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const u32 kvm_cpuid_7_0_ebx_x86_features =
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F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
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F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
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F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) |
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F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
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F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | f_intel_pt;
|
|
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/* cpuid 0xD.1.eax */
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const u32 kvm_cpuid_D_1_eax_x86_features =
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F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | f_xsaves;
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|
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/* cpuid 7.0.ecx*/
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const u32 kvm_cpuid_7_0_ecx_x86_features =
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F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ |
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F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
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F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
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F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B);
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|
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/* cpuid 7.0.edx*/
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const u32 kvm_cpuid_7_0_edx_x86_features =
|
|
F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
|
|
F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP);
|
|
|
|
/* all calls to cpuid_count() should be made on the same cpu */
|
|
get_cpu();
|
|
|
|
r = -E2BIG;
|
|
|
|
if (*nent >= maxnent)
|
|
goto out;
|
|
|
|
do_cpuid_1_ent(entry, function, index);
|
|
++*nent;
|
|
|
|
switch (function) {
|
|
case 0:
|
|
entry->eax = min(entry->eax, (u32)(f_intel_pt ? 0x14 : 0xd));
|
|
break;
|
|
case 1:
|
|
entry->edx &= kvm_cpuid_1_edx_x86_features;
|
|
cpuid_mask(&entry->edx, CPUID_1_EDX);
|
|
entry->ecx &= kvm_cpuid_1_ecx_x86_features;
|
|
cpuid_mask(&entry->ecx, CPUID_1_ECX);
|
|
/* we support x2apic emulation even if host does not support
|
|
* it since we emulate x2apic in software */
|
|
entry->ecx |= F(X2APIC);
|
|
break;
|
|
/* function 2 entries are STATEFUL. That is, repeated cpuid commands
|
|
* may return different values. This forces us to get_cpu() before
|
|
* issuing the first command, and also to emulate this annoying behavior
|
|
* in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
|
|
case 2: {
|
|
int t, times = entry->eax & 0xff;
|
|
|
|
entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
|
|
entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
|
|
for (t = 1; t < times; ++t) {
|
|
if (*nent >= maxnent)
|
|
goto out;
|
|
|
|
do_cpuid_1_ent(&entry[t], function, 0);
|
|
entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
|
|
++*nent;
|
|
}
|
|
break;
|
|
}
|
|
/* function 4 has additional index. */
|
|
case 4: {
|
|
int i, cache_type;
|
|
|
|
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
/* read more entries until cache_type is zero */
|
|
for (i = 1; ; ++i) {
|
|
if (*nent >= maxnent)
|
|
goto out;
|
|
|
|
cache_type = entry[i - 1].eax & 0x1f;
|
|
if (!cache_type)
|
|
break;
|
|
do_cpuid_1_ent(&entry[i], function, i);
|
|
entry[i].flags |=
|
|
KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
++*nent;
|
|
}
|
|
break;
|
|
}
|
|
case 6: /* Thermal management */
|
|
entry->eax = 0x4; /* allow ARAT */
|
|
entry->ebx = 0;
|
|
entry->ecx = 0;
|
|
entry->edx = 0;
|
|
break;
|
|
case 7: {
|
|
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
/* Mask ebx against host capability word 9 */
|
|
if (index == 0) {
|
|
entry->ebx &= kvm_cpuid_7_0_ebx_x86_features;
|
|
cpuid_mask(&entry->ebx, CPUID_7_0_EBX);
|
|
// TSC_ADJUST is emulated
|
|
entry->ebx |= F(TSC_ADJUST);
|
|
entry->ecx &= kvm_cpuid_7_0_ecx_x86_features;
|
|
cpuid_mask(&entry->ecx, CPUID_7_ECX);
|
|
entry->ecx |= f_umip;
|
|
/* PKU is not yet implemented for shadow paging. */
|
|
if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
|
|
entry->ecx &= ~F(PKU);
|
|
entry->edx &= kvm_cpuid_7_0_edx_x86_features;
|
|
cpuid_mask(&entry->edx, CPUID_7_EDX);
|
|
/*
|
|
* We emulate ARCH_CAPABILITIES in software even
|
|
* if the host doesn't support it.
|
|
*/
|
|
entry->edx |= F(ARCH_CAPABILITIES);
|
|
} else {
|
|
entry->ebx = 0;
|
|
entry->ecx = 0;
|
|
entry->edx = 0;
|
|
}
|
|
entry->eax = 0;
|
|
break;
|
|
}
|
|
case 9:
|
|
break;
|
|
case 0xa: { /* Architectural Performance Monitoring */
|
|
struct x86_pmu_capability cap;
|
|
union cpuid10_eax eax;
|
|
union cpuid10_edx edx;
|
|
|
|
perf_get_x86_pmu_capability(&cap);
|
|
|
|
/*
|
|
* Only support guest architectural pmu on a host
|
|
* with architectural pmu.
|
|
*/
|
|
if (!cap.version)
|
|
memset(&cap, 0, sizeof(cap));
|
|
|
|
eax.split.version_id = min(cap.version, 2);
|
|
eax.split.num_counters = cap.num_counters_gp;
|
|
eax.split.bit_width = cap.bit_width_gp;
|
|
eax.split.mask_length = cap.events_mask_len;
|
|
|
|
edx.split.num_counters_fixed = cap.num_counters_fixed;
|
|
edx.split.bit_width_fixed = cap.bit_width_fixed;
|
|
edx.split.reserved = 0;
|
|
|
|
entry->eax = eax.full;
|
|
entry->ebx = cap.events_mask;
|
|
entry->ecx = 0;
|
|
entry->edx = edx.full;
|
|
break;
|
|
}
|
|
/* function 0xb has additional index. */
|
|
case 0xb: {
|
|
int i, level_type;
|
|
|
|
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
/* read more entries until level_type is zero */
|
|
for (i = 1; ; ++i) {
|
|
if (*nent >= maxnent)
|
|
goto out;
|
|
|
|
level_type = entry[i - 1].ecx & 0xff00;
|
|
if (!level_type)
|
|
break;
|
|
do_cpuid_1_ent(&entry[i], function, i);
|
|
entry[i].flags |=
|
|
KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
++*nent;
|
|
}
|
|
break;
|
|
}
|
|
case 0xd: {
|
|
int idx, i;
|
|
u64 supported = kvm_supported_xcr0();
|
|
|
|
entry->eax &= supported;
|
|
entry->ebx = xstate_required_size(supported, false);
|
|
entry->ecx = entry->ebx;
|
|
entry->edx &= supported >> 32;
|
|
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
if (!supported)
|
|
break;
|
|
|
|
for (idx = 1, i = 1; idx < 64; ++idx) {
|
|
u64 mask = ((u64)1 << idx);
|
|
if (*nent >= maxnent)
|
|
goto out;
|
|
|
|
do_cpuid_1_ent(&entry[i], function, idx);
|
|
if (idx == 1) {
|
|
entry[i].eax &= kvm_cpuid_D_1_eax_x86_features;
|
|
cpuid_mask(&entry[i].eax, CPUID_D_1_EAX);
|
|
entry[i].ebx = 0;
|
|
if (entry[i].eax & (F(XSAVES)|F(XSAVEC)))
|
|
entry[i].ebx =
|
|
xstate_required_size(supported,
|
|
true);
|
|
} else {
|
|
if (entry[i].eax == 0 || !(supported & mask))
|
|
continue;
|
|
if (WARN_ON_ONCE(entry[i].ecx & 1))
|
|
continue;
|
|
}
|
|
entry[i].ecx = 0;
|
|
entry[i].edx = 0;
|
|
entry[i].flags |=
|
|
KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
++*nent;
|
|
++i;
|
|
}
|
|
break;
|
|
}
|
|
/* Intel PT */
|
|
case 0x14: {
|
|
int t, times = entry->eax;
|
|
|
|
if (!f_intel_pt)
|
|
break;
|
|
|
|
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
for (t = 1; t <= times; ++t) {
|
|
if (*nent >= maxnent)
|
|
goto out;
|
|
do_cpuid_1_ent(&entry[t], function, t);
|
|
entry[t].flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
++*nent;
|
|
}
|
|
break;
|
|
}
|
|
case KVM_CPUID_SIGNATURE: {
|
|
static const char signature[12] = "KVMKVMKVM\0\0";
|
|
const u32 *sigptr = (const u32 *)signature;
|
|
entry->eax = KVM_CPUID_FEATURES;
|
|
entry->ebx = sigptr[0];
|
|
entry->ecx = sigptr[1];
|
|
entry->edx = sigptr[2];
|
|
break;
|
|
}
|
|
case KVM_CPUID_FEATURES:
|
|
entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
|
|
(1 << KVM_FEATURE_NOP_IO_DELAY) |
|
|
(1 << KVM_FEATURE_CLOCKSOURCE2) |
|
|
(1 << KVM_FEATURE_ASYNC_PF) |
|
|
(1 << KVM_FEATURE_PV_EOI) |
|
|
(1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
|
|
(1 << KVM_FEATURE_PV_UNHALT) |
|
|
(1 << KVM_FEATURE_PV_TLB_FLUSH) |
|
|
(1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
|
|
(1 << KVM_FEATURE_PV_SEND_IPI);
|
|
|
|
if (sched_info_on())
|
|
entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
|
|
|
|
entry->ebx = 0;
|
|
entry->ecx = 0;
|
|
entry->edx = 0;
|
|
break;
|
|
case 0x80000000:
|
|
entry->eax = min(entry->eax, 0x8000001f);
|
|
break;
|
|
case 0x80000001:
|
|
entry->edx &= kvm_cpuid_8000_0001_edx_x86_features;
|
|
cpuid_mask(&entry->edx, CPUID_8000_0001_EDX);
|
|
entry->ecx &= kvm_cpuid_8000_0001_ecx_x86_features;
|
|
cpuid_mask(&entry->ecx, CPUID_8000_0001_ECX);
|
|
break;
|
|
case 0x80000007: /* Advanced power management */
|
|
/* invariant TSC is CPUID.80000007H:EDX[8] */
|
|
entry->edx &= (1 << 8);
|
|
/* mask against host */
|
|
entry->edx &= boot_cpu_data.x86_power;
|
|
entry->eax = entry->ebx = entry->ecx = 0;
|
|
break;
|
|
case 0x80000008: {
|
|
unsigned g_phys_as = (entry->eax >> 16) & 0xff;
|
|
unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
|
|
unsigned phys_as = entry->eax & 0xff;
|
|
|
|
if (!g_phys_as)
|
|
g_phys_as = phys_as;
|
|
entry->eax = g_phys_as | (virt_as << 8);
|
|
entry->edx = 0;
|
|
/*
|
|
* IBRS, IBPB and VIRT_SSBD aren't necessarily present in
|
|
* hardware cpuid
|
|
*/
|
|
if (boot_cpu_has(X86_FEATURE_AMD_IBPB))
|
|
entry->ebx |= F(AMD_IBPB);
|
|
if (boot_cpu_has(X86_FEATURE_AMD_IBRS))
|
|
entry->ebx |= F(AMD_IBRS);
|
|
if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
|
|
entry->ebx |= F(VIRT_SSBD);
|
|
entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;
|
|
cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);
|
|
/*
|
|
* The preference is to use SPEC CTRL MSR instead of the
|
|
* VIRT_SPEC MSR.
|
|
*/
|
|
if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
|
|
!boot_cpu_has(X86_FEATURE_AMD_SSBD))
|
|
entry->ebx |= F(VIRT_SSBD);
|
|
break;
|
|
}
|
|
case 0x80000019:
|
|
entry->ecx = entry->edx = 0;
|
|
break;
|
|
case 0x8000001a:
|
|
break;
|
|
case 0x8000001d:
|
|
break;
|
|
/*Add support for Centaur's CPUID instruction*/
|
|
case 0xC0000000:
|
|
/*Just support up to 0xC0000004 now*/
|
|
entry->eax = min(entry->eax, 0xC0000004);
|
|
break;
|
|
case 0xC0000001:
|
|
entry->edx &= kvm_cpuid_C000_0001_edx_x86_features;
|
|
cpuid_mask(&entry->edx, CPUID_C000_0001_EDX);
|
|
break;
|
|
case 3: /* Processor serial number */
|
|
case 5: /* MONITOR/MWAIT */
|
|
case 0xC0000002:
|
|
case 0xC0000003:
|
|
case 0xC0000004:
|
|
default:
|
|
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
|
|
break;
|
|
}
|
|
|
|
kvm_x86_ops->set_supported_cpuid(function, entry);
|
|
|
|
r = 0;
|
|
|
|
out:
|
|
put_cpu();
|
|
|
|
return r;
|
|
}
|
|
|
|
static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 func,
|
|
u32 idx, int *nent, int maxnent, unsigned int type)
|
|
{
|
|
if (type == KVM_GET_EMULATED_CPUID)
|
|
return __do_cpuid_ent_emulated(entry, func, idx, nent, maxnent);
|
|
|
|
return __do_cpuid_ent(entry, func, idx, nent, maxnent);
|
|
}
|
|
|
|
#undef F
|
|
|
|
struct kvm_cpuid_param {
|
|
u32 func;
|
|
u32 idx;
|
|
bool has_leaf_count;
|
|
bool (*qualifier)(const struct kvm_cpuid_param *param);
|
|
};
|
|
|
|
static bool is_centaur_cpu(const struct kvm_cpuid_param *param)
|
|
{
|
|
return boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR;
|
|
}
|
|
|
|
static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
|
|
__u32 num_entries, unsigned int ioctl_type)
|
|
{
|
|
int i;
|
|
__u32 pad[3];
|
|
|
|
if (ioctl_type != KVM_GET_EMULATED_CPUID)
|
|
return false;
|
|
|
|
/*
|
|
* We want to make sure that ->padding is being passed clean from
|
|
* userspace in case we want to use it for something in the future.
|
|
*
|
|
* Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
|
|
* have to give ourselves satisfied only with the emulated side. /me
|
|
* sheds a tear.
|
|
*/
|
|
for (i = 0; i < num_entries; i++) {
|
|
if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
|
|
return true;
|
|
|
|
if (pad[0] || pad[1] || pad[2])
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
|
|
struct kvm_cpuid_entry2 __user *entries,
|
|
unsigned int type)
|
|
{
|
|
struct kvm_cpuid_entry2 *cpuid_entries;
|
|
int limit, nent = 0, r = -E2BIG, i;
|
|
u32 func;
|
|
static const struct kvm_cpuid_param param[] = {
|
|
{ .func = 0, .has_leaf_count = true },
|
|
{ .func = 0x80000000, .has_leaf_count = true },
|
|
{ .func = 0xC0000000, .qualifier = is_centaur_cpu, .has_leaf_count = true },
|
|
{ .func = KVM_CPUID_SIGNATURE },
|
|
{ .func = KVM_CPUID_FEATURES },
|
|
};
|
|
|
|
if (cpuid->nent < 1)
|
|
goto out;
|
|
if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
|
|
cpuid->nent = KVM_MAX_CPUID_ENTRIES;
|
|
|
|
if (sanity_check_entries(entries, cpuid->nent, type))
|
|
return -EINVAL;
|
|
|
|
r = -ENOMEM;
|
|
cpuid_entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2),
|
|
cpuid->nent));
|
|
if (!cpuid_entries)
|
|
goto out;
|
|
|
|
r = 0;
|
|
for (i = 0; i < ARRAY_SIZE(param); i++) {
|
|
const struct kvm_cpuid_param *ent = ¶m[i];
|
|
|
|
if (ent->qualifier && !ent->qualifier(ent))
|
|
continue;
|
|
|
|
r = do_cpuid_ent(&cpuid_entries[nent], ent->func, ent->idx,
|
|
&nent, cpuid->nent, type);
|
|
|
|
if (r)
|
|
goto out_free;
|
|
|
|
if (!ent->has_leaf_count)
|
|
continue;
|
|
|
|
limit = cpuid_entries[nent - 1].eax;
|
|
for (func = ent->func + 1; func <= limit && nent < cpuid->nent && r == 0; ++func)
|
|
r = do_cpuid_ent(&cpuid_entries[nent], func, ent->idx,
|
|
&nent, cpuid->nent, type);
|
|
|
|
if (r)
|
|
goto out_free;
|
|
}
|
|
|
|
r = -EFAULT;
|
|
if (copy_to_user(entries, cpuid_entries,
|
|
nent * sizeof(struct kvm_cpuid_entry2)))
|
|
goto out_free;
|
|
cpuid->nent = nent;
|
|
r = 0;
|
|
|
|
out_free:
|
|
vfree(cpuid_entries);
|
|
out:
|
|
return r;
|
|
}
|
|
|
|
static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
|
|
{
|
|
struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
|
|
struct kvm_cpuid_entry2 *ej;
|
|
int j = i;
|
|
int nent = vcpu->arch.cpuid_nent;
|
|
|
|
e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
|
|
/* when no next entry is found, the current entry[i] is reselected */
|
|
do {
|
|
j = (j + 1) % nent;
|
|
ej = &vcpu->arch.cpuid_entries[j];
|
|
} while (ej->function != e->function);
|
|
|
|
ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
|
|
|
|
return j;
|
|
}
|
|
|
|
/* find an entry with matching function, matching index (if needed), and that
|
|
* should be read next (if it's stateful) */
|
|
static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
|
|
u32 function, u32 index)
|
|
{
|
|
if (e->function != function)
|
|
return 0;
|
|
if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
|
|
return 0;
|
|
if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
|
|
!(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
|
|
return 0;
|
|
return 1;
|
|
}
|
|
|
|
struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
|
|
u32 function, u32 index)
|
|
{
|
|
int i;
|
|
struct kvm_cpuid_entry2 *best = NULL;
|
|
|
|
for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
|
|
struct kvm_cpuid_entry2 *e;
|
|
|
|
e = &vcpu->arch.cpuid_entries[i];
|
|
if (is_matching_cpuid_entry(e, function, index)) {
|
|
if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
|
|
move_to_next_stateful_cpuid_entry(vcpu, i);
|
|
best = e;
|
|
break;
|
|
}
|
|
}
|
|
return best;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
|
|
|
|
/*
|
|
* If no match is found, check whether we exceed the vCPU's limit
|
|
* and return the content of the highest valid _standard_ leaf instead.
|
|
* This is to satisfy the CPUID specification.
|
|
*/
|
|
static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
|
|
u32 function, u32 index)
|
|
{
|
|
struct kvm_cpuid_entry2 *maxlevel;
|
|
|
|
maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
|
|
if (!maxlevel || maxlevel->eax >= function)
|
|
return NULL;
|
|
if (function & 0x80000000) {
|
|
maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
|
|
if (!maxlevel)
|
|
return NULL;
|
|
}
|
|
return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
|
|
}
|
|
|
|
bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
|
|
u32 *ecx, u32 *edx, bool check_limit)
|
|
{
|
|
u32 function = *eax, index = *ecx;
|
|
struct kvm_cpuid_entry2 *best;
|
|
bool entry_found = true;
|
|
|
|
best = kvm_find_cpuid_entry(vcpu, function, index);
|
|
|
|
if (!best) {
|
|
entry_found = false;
|
|
if (!check_limit)
|
|
goto out;
|
|
|
|
best = check_cpuid_limit(vcpu, function, index);
|
|
}
|
|
|
|
out:
|
|
if (best) {
|
|
*eax = best->eax;
|
|
*ebx = best->ebx;
|
|
*ecx = best->ecx;
|
|
*edx = best->edx;
|
|
} else
|
|
*eax = *ebx = *ecx = *edx = 0;
|
|
trace_kvm_cpuid(function, *eax, *ebx, *ecx, *edx, entry_found);
|
|
return entry_found;
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_cpuid);
|
|
|
|
int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
|
|
{
|
|
u32 eax, ebx, ecx, edx;
|
|
|
|
if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
|
|
return 1;
|
|
|
|
eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
|
|
ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
|
|
kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, true);
|
|
kvm_register_write(vcpu, VCPU_REGS_RAX, eax);
|
|
kvm_register_write(vcpu, VCPU_REGS_RBX, ebx);
|
|
kvm_register_write(vcpu, VCPU_REGS_RCX, ecx);
|
|
kvm_register_write(vcpu, VCPU_REGS_RDX, edx);
|
|
return kvm_skip_emulated_instruction(vcpu);
|
|
}
|
|
EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
|