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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f8e798a9e2
Use macro IO_ADDRESS for getting virtual address of corresponding physical address to make the consistency with rest of Tegra code-base. This macro calls the IO_TO_VIRT() which is defined in arch/arm/mach-tegra/include/mach/iomap.h Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
/*
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* arch/arm/mach-tegra/fuse.c
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <mach/iomap.h>
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#include "fuse.h"
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#include "apbio.h"
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#define FUSE_UID_LOW 0x108
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#define FUSE_UID_HIGH 0x10c
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#define FUSE_SKU_INFO 0x110
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#define FUSE_SPARE_BIT 0x200
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int tegra_sku_id;
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int tegra_cpu_process_id;
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int tegra_core_process_id;
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int tegra_chip_id;
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enum tegra_revision tegra_revision;
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/* The BCT to use at boot is specified by board straps that can be read
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* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
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*/
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int tegra_bct_strapping;
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#define STRAP_OPT 0x008
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#define GMI_AD0 (1 << 4)
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#define GMI_AD1 (1 << 5)
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#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
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#define RAM_CODE_SHIFT 4
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static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
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[TEGRA_REVISION_UNKNOWN] = "unknown",
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[TEGRA_REVISION_A01] = "A01",
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[TEGRA_REVISION_A02] = "A02",
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[TEGRA_REVISION_A03] = "A03",
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[TEGRA_REVISION_A03p] = "A03 prime",
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[TEGRA_REVISION_A04] = "A04",
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};
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static inline u32 tegra_fuse_readl(unsigned long offset)
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{
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return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
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}
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static inline bool get_spare_fuse(int bit)
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{
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return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
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}
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static enum tegra_revision tegra_get_revision(u32 id)
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{
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u32 minor_rev = (id >> 16) & 0xf;
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switch (minor_rev) {
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case 1:
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return TEGRA_REVISION_A01;
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case 2:
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return TEGRA_REVISION_A02;
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case 3:
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if (tegra_chip_id == TEGRA20 &&
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(get_spare_fuse(18) || get_spare_fuse(19)))
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return TEGRA_REVISION_A03p;
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else
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return TEGRA_REVISION_A03;
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case 4:
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return TEGRA_REVISION_A04;
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default:
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return TEGRA_REVISION_UNKNOWN;
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}
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}
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void tegra_init_fuse(void)
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{
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u32 id;
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u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
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reg |= 1 << 28;
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writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
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reg = tegra_fuse_readl(FUSE_SKU_INFO);
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tegra_sku_id = reg & 0xFF;
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reg = tegra_fuse_readl(FUSE_SPARE_BIT);
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tegra_cpu_process_id = (reg >> 6) & 3;
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reg = tegra_fuse_readl(FUSE_SPARE_BIT);
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tegra_core_process_id = (reg >> 12) & 3;
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reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
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tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
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id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
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tegra_chip_id = (id >> 8) & 0xff;
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tegra_revision = tegra_get_revision(id);
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pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
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tegra_revision_name[tegra_revision],
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tegra_sku_id, tegra_cpu_process_id,
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tegra_core_process_id);
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}
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unsigned long long tegra_chip_uid(void)
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{
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unsigned long long lo, hi;
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lo = tegra_fuse_readl(FUSE_UID_LOW);
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hi = tegra_fuse_readl(FUSE_UID_HIGH);
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return (hi << 32ull) | lo;
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}
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EXPORT_SYMBOL(tegra_chip_uid);
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