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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
81 lines
1.7 KiB
ArmAsm
81 lines
1.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* vDSO provided cache flush routines
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*
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* Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
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* IBM Corp.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/vdso.h>
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#include <asm/asm-offsets.h>
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.text
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/*
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* Default "generic" version of __kernel_sync_dicache.
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*
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* void __kernel_sync_dicache(unsigned long start, unsigned long end)
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*
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* Flushes the data cache & invalidate the instruction cache for the
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* provided range [start, end[
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*/
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V_FUNCTION_BEGIN(__kernel_sync_dicache)
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.cfi_startproc
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mflr r12
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.cfi_register lr,r12
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mr r11,r3
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bl V_LOCAL_FUNC(__get_datapage)
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mtlr r12
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mr r10,r3
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lwz r7,CFG_DCACHE_BLOCKSZ(r10)
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addi r5,r7,-1
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andc r6,r11,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5 /* ensure we get enough */
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lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
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srw. r8,r8,r9 /* compute line count */
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crclr cr0*4+so
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beqlr /* nothing to do? */
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mtctr r8
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1: dcbst 0,r6
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add r6,r6,r7
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bdnz 1b
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sync
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/* Now invalidate the instruction cache */
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lwz r7,CFG_ICACHE_BLOCKSZ(r10)
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addi r5,r7,-1
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andc r6,r11,r5 /* round low to line bdy */
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subf r8,r6,r4 /* compute length */
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add r8,r8,r5
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lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
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srw. r8,r8,r9 /* compute line count */
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crclr cr0*4+so
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beqlr /* nothing to do? */
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mtctr r8
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2: icbi 0,r6
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add r6,r6,r7
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bdnz 2b
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isync
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li r3,0
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blr
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.cfi_endproc
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V_FUNCTION_END(__kernel_sync_dicache)
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/*
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* POWER5 version of __kernel_sync_dicache
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*/
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V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
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.cfi_startproc
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crclr cr0*4+so
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sync
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isync
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li r3,0
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blr
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.cfi_endproc
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V_FUNCTION_END(__kernel_sync_dicache_p5)
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