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Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
91 lines
1.8 KiB
Plaintext
91 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*/
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/dts-v1/;
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/include/ "skeleton_hs.dtsi"
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/ {
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model = "snps,nsimosci_hs";
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compatible = "snps,nsimosci_hs";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&core_intc>;
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chosen {
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/* this is for console on PGU */
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/* bootargs = "console=tty0 consoleblank=0"; */
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/* this is for console on serial */
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bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
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};
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aliases {
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serial0 = &uart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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uart0: serial@f0000000 {
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compatible = "ns8250";
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reg = <0xf0000000 0x2000>;
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interrupts = <24>;
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clock-frequency = <3686400>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test = <1>;
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};
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pguclk: pguclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25175000>;
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};
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pgu@f9000000 {
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compatible = "snps,arcpgu";
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reg = <0xf9000000 0x400>;
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clocks = <&pguclk>;
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clock-names = "pxlclk";
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};
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ps2: ps2@f9001000 {
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compatible = "snps,arc_ps2";
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reg = <0xf9000400 0x14>;
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interrupts = <27>;
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interrupt-names = "arc_ps2_irq";
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};
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eth0: ethernet@f0003000 {
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compatible = "ezchip,nps-mgt-enet";
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reg = <0xf0003000 0x44>;
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interrupts = <25>;
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};
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arcpct0: pct {
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compatible = "snps,archs-pct";
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#interrupt-cells = <1>;
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interrupts = <20>;
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};
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};
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};
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