Stephane Eranian 20a36e39d5 perf/x86: Fix Intel Ivy Bridge support ... This patch updates the existing Intel IvyBridge (model 58) support with proper PEBS event constraints. It cannot reuse the same as SandyBridge because some events (0xd3) are specific to IvyBridge. Also there is no UOPS_DISPATCHED.THREAD on IVB, so do not populate the PERF_COUNT_HW_STALLED_CYCLES_BACKEND mapping. Signed-off-by: Stephane Eranian <eranian@google.com> Cc: peterz@infradead.org Cc: ak@linux.intel.com Link: http://lkml.kernel.org/r/20120910230701.GA5898@quad Signed-off-by: Ingo Molnar <mingo@kernel.org>		2012-09-19 17:28:47 +02:00
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mcheck	Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2012-08-03 10:59:36 -07:00
mtrr	x86/mm/mtrr: Slightly simplify print_mtrr_state()	2012-07-10 10:38:15 +02:00
.gitignore	Update .gitignore files for generated targets	2008-10-20 11:24:31 -07:00
amd.c	x86, cpu: Rename checking_wrmsrl() to wrmsrl_safe()	2012-06-07 13:32:04 -07:00
bugs_64.c	x86/cpu: Clean up various files a bit	2009-07-11 11:24:09 +02:00
bugs.c	x86/debug: Add KERN_<LEVEL> to bare printks, convert printks to pr_<level>	2012-06-06 09:17:22 +02:00
centaur.c	x86, centaur: Enable cx8 for VIA Eden too	2011-12-15 08:04:42 -08:00
common.c	x86, avx: don't use avx instructions with "noxsave" boot param	2012-08-08 13:41:42 -07:00
cpu.h	x86/tlb_info: get last level TLB entry number of CPU	2012-06-27 19:28:24 -07:00
cyrix.c	x86, cpu: mv display_cacheinfo -> cpu_detect_cache_sizes	2009-11-23 11:59:53 -08:00
hypervisor.c	x86, hyper: fix build with !CONFIG_KVM_GUEST	2012-07-18 17:01:48 -03:00
intel_cacheinfo.c	x86/cache_info: Fix setup of l2/l3 ids	2012-05-07 15:27:37 +02:00
intel.c	x86/tlb: add tlb_flushall_shift for specific CPU	2012-06-27 19:29:10 -07:00
Makefile	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2012-07-26 13:08:01 -07:00
match.c	x86: Fix typo in MODULE_DEVICE_TABLE example: s/x86_cpu/x86cpu/	2012-04-16 14:20:19 +02:00
mkcapflags.pl	x86, cpufeature: Remove stray %s, add -w to mkcapflags.pl	2012-06-26 08:02:48 -07:00
mshyperv.c	x86: Hyper-V: Integrate the clocksource with Hyper-V detection code	2011-09-08 10:33:59 +02:00
perf_event_amd_ibs.c	perf/x86/ibs: Check syscall attribute flags	2012-09-13 16:59:48 +02:00
perf_event_amd.c	perf/x86/amd: Unify AMD's generic and family 15h pmus	2012-07-05 21:19:41 +02:00
perf_event_intel_ds.c	perf/x86: Fix Intel Ivy Bridge support	2012-09-19 17:28:47 +02:00
perf_event_intel_lbr.c	perf/x86: Enable Intel Cedarview Atom suppport	2012-09-04 17:29:23 +02:00
perf_event_intel_uncore.c	perf/x86: Export Sandy Bridge uncore clockticks event in sysfs	2012-09-13 16:59:46 +02:00
perf_event_intel_uncore.h	perf/x86: Add Intel Westmere-EX uncore support	2012-08-13 19:01:04 +02:00
perf_event_intel.c	perf/x86: Fix Intel Ivy Bridge support	2012-09-19 17:28:47 +02:00
perf_event_p4.c	perf/x86: Rename Intel specific macros	2012-07-05 21:19:39 +02:00
perf_event_p6.c	x86, cpu: Rename checking_wrmsrl() to wrmsrl_safe()	2012-06-07 13:32:04 -07:00
perf_event.c	perf/x86: Fix USER/KERNEL tagging of samples properly	2012-07-31 17:02:04 +02:00
perf_event.h	perf/x86: Fix Intel Ivy Bridge support	2012-09-19 17:28:47 +02:00
perfctr-watchdog.c	perf, x86: Add new AMD family 15h msrs to perfctr reservation code	2011-02-16 13:30:50 +01:00
powerflags.c	x86: Report cpb and eff_freq_ro flags correctly	2011-12-15 08:14:49 +01:00
proc.c	x86: Simplify code by removing a !SMP #ifdefs from 'struct cpuinfo_x86'	2011-12-21 09:25:09 +01:00
rdrand.c	x86, random: Verify RDRAND functionality and allow it to be disabled	2011-07-31 14:02:19 -07:00
scattered.c	x86, cpufeature: Rename X86_FEATURE_DTS to X86_FEATURE_DTHERM	2012-06-25 09:01:15 -07:00
topology.c	x86, cpu: Split addon_cpuid_features.c	2010-07-19 19:02:41 -07:00
transmeta.c	x86, cpu: mv display_cacheinfo -> cpu_detect_cache_sizes	2009-11-23 11:59:53 -08:00
umc.c	x86: move various CPU initialization objects into .cpuinit.rodata	2009-03-12 13:13:07 +01:00
vmware.c	x86: Fix common misspellings	2011-03-18 10:39:30 +01:00