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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1e02ce4ccc
Context switches and TLB flushes can change individual bits of CR4. CR4 reads take several cycles, so store a shadow copy of CR4 in a per-cpu variable. To avoid wasting a cache line, I added the CR4 shadow to cpu_tlbstate, which is already touched in switch_mm. The heaviest users of the cr4 shadow will be switch_mm and __switch_to_xtra, and __switch_to_xtra is called shortly after switch_mm during context switch, so the cacheline is likely to be hot. Signed-off-by: Andy Lutomirski <luto@amacapital.net> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Kees Cook <keescook@chromium.org> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Vince Weaver <vince@deater.net> Cc: "hillf.zj" <hillf.zj@alibaba-inc.com> Cc: Valdis Kletnieks <Valdis.Kletnieks@vt.edu> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/3a54dd3353fffbf84804398e00dfdc5b7c1afd7d.1414190806.git.luto@amacapital.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
141 lines
3.8 KiB
C
141 lines
3.8 KiB
C
/*
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* sleep.c - x86-specific ACPI sleep support.
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*
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* Copyright (C) 2001-2003 Patrick Mochel
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* Copyright (C) 2001-2003 Pavel Machek <pavel@ucw.cz>
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*/
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#include <linux/acpi.h>
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#include <linux/bootmem.h>
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#include <linux/memblock.h>
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#include <linux/dmi.h>
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#include <linux/cpumask.h>
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#include <asm/segment.h>
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#include <asm/desc.h>
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#include <asm/realmode.h>
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#include "../../realmode/rm/wakeup.h"
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#include "sleep.h"
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unsigned long acpi_realmode_flags;
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#if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
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static char temp_stack[4096];
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#endif
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/**
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* x86_acpi_enter_sleep_state - enter sleep state
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* @state: Sleep state to enter.
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*
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* Wrapper around acpi_enter_sleep_state() to be called by assmebly.
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*/
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acpi_status asmlinkage __visible x86_acpi_enter_sleep_state(u8 state)
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{
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return acpi_enter_sleep_state(state);
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}
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/**
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* x86_acpi_suspend_lowlevel - save kernel state
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*
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* Create an identity mapped page table and copy the wakeup routine to
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* low memory.
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*/
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int x86_acpi_suspend_lowlevel(void)
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{
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struct wakeup_header *header =
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(struct wakeup_header *) __va(real_mode_header->wakeup_header);
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if (header->signature != WAKEUP_HEADER_SIGNATURE) {
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printk(KERN_ERR "wakeup header does not match\n");
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return -EINVAL;
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}
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header->video_mode = saved_video_mode;
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header->pmode_behavior = 0;
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#ifndef CONFIG_64BIT
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native_store_gdt((struct desc_ptr *)&header->pmode_gdt);
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/*
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* We have to check that we can write back the value, and not
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* just read it. At least on 90 nm Pentium M (Family 6, Model
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* 13), reading an invalid MSR is not guaranteed to trap, see
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* Erratum X4 in "Intel Pentium M Processor on 90 nm Process
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* with 2-MB L2 Cache and Intel® Processor A100 and A110 on 90
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* nm process with 512-KB L2 Cache Specification Update".
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*/
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if (!rdmsr_safe(MSR_EFER,
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&header->pmode_efer_low,
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&header->pmode_efer_high) &&
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!wrmsr_safe(MSR_EFER,
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header->pmode_efer_low,
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header->pmode_efer_high))
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header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_EFER);
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#endif /* !CONFIG_64BIT */
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header->pmode_cr0 = read_cr0();
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if (__this_cpu_read(cpu_info.cpuid_level) >= 0) {
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header->pmode_cr4 = __read_cr4();
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header->pmode_behavior |= (1 << WAKEUP_BEHAVIOR_RESTORE_CR4);
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}
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if (!rdmsr_safe(MSR_IA32_MISC_ENABLE,
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&header->pmode_misc_en_low,
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&header->pmode_misc_en_high) &&
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!wrmsr_safe(MSR_IA32_MISC_ENABLE,
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header->pmode_misc_en_low,
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header->pmode_misc_en_high))
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header->pmode_behavior |=
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(1 << WAKEUP_BEHAVIOR_RESTORE_MISC_ENABLE);
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header->realmode_flags = acpi_realmode_flags;
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header->real_magic = 0x12345678;
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#ifndef CONFIG_64BIT
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header->pmode_entry = (u32)&wakeup_pmode_return;
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header->pmode_cr3 = (u32)__pa_symbol(initial_page_table);
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saved_magic = 0x12345678;
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#else /* CONFIG_64BIT */
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#ifdef CONFIG_SMP
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stack_start = (unsigned long)temp_stack + sizeof(temp_stack);
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early_gdt_descr.address =
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(unsigned long)get_cpu_gdt_table(smp_processor_id());
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initial_gs = per_cpu_offset(smp_processor_id());
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#endif
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initial_code = (unsigned long)wakeup_long64;
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saved_magic = 0x123456789abcdef0L;
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#endif /* CONFIG_64BIT */
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do_suspend_lowlevel();
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return 0;
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}
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static int __init acpi_sleep_setup(char *str)
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{
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while ((str != NULL) && (*str != '\0')) {
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if (strncmp(str, "s3_bios", 7) == 0)
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acpi_realmode_flags |= 1;
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if (strncmp(str, "s3_mode", 7) == 0)
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acpi_realmode_flags |= 2;
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if (strncmp(str, "s3_beep", 7) == 0)
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acpi_realmode_flags |= 4;
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#ifdef CONFIG_HIBERNATION
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if (strncmp(str, "s4_nohwsig", 10) == 0)
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acpi_no_s4_hw_signature();
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#endif
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if (strncmp(str, "nonvs", 5) == 0)
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acpi_nvs_nosave();
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if (strncmp(str, "nonvs_s3", 8) == 0)
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acpi_nvs_nosave_s3();
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if (strncmp(str, "old_ordering", 12) == 0)
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acpi_old_suspend_ordering();
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str = strchr(str, ',');
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if (str != NULL)
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str += strspn(str, ", \t");
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}
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return 1;
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}
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__setup("acpi_sleep=", acpi_sleep_setup);
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