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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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687c27b070
Tie in the APMU SMP code on r8a7791. When used together with the secondary CPU device node and smp_ops in the board specific code then this will allow use of the two Cortex-A15 cores in the r8a7791 SoC. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
185 lines
5.8 KiB
C
185 lines
5.8 KiB
C
/*
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* r8a7791 processor support
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a7791.h>
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#include <mach/rcar-gen2.h>
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#include <asm/mach/arch.h>
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#define SCIF_COMMON(scif_type, baseaddr, irq) \
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.type = scif_type, \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.irqs = SCIx_IRQ_MUXED(irq)
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#define SCIFA_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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#define SCIFB_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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#define SCIF_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_2, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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#define HSCIF_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_6, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
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SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
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static const struct plat_sci_port scif[] __initconst = {
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SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
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SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
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SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
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SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
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SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
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SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
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SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
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SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
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SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
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SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
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SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
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SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
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SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
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SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
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SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
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};
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static inline void r8a7791_register_scif(int idx)
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{
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platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
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sizeof(struct plat_sci_port));
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}
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static const struct sh_timer_config cmt00_platform_data __initconst = {
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.name = "CMT00",
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.timer_bit = 0,
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.clockevent_rating = 80,
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};
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static const struct resource cmt00_resources[] __initconst = {
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DEFINE_RES_MEM(0xffca0510, 0x0c),
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DEFINE_RES_MEM(0xffca0500, 0x04),
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DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
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};
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#define r8a7791_register_cmt(idx) \
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platform_device_register_resndata(&platform_bus, "sh_cmt", \
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idx, cmt##idx##_resources, \
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ARRAY_SIZE(cmt##idx##_resources), \
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&cmt##idx##_platform_data, \
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sizeof(struct sh_timer_config))
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static struct renesas_irqc_config irqc0_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
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};
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static struct resource irqc0_resources[] = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
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DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
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DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
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DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
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DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
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DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
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};
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#define r8a7791_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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void __init r8a7791_add_dt_devices(void)
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{
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r8a7791_register_scif(SCIFA0);
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r8a7791_register_scif(SCIFA1);
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r8a7791_register_scif(SCIFB0);
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r8a7791_register_scif(SCIFB1);
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r8a7791_register_scif(SCIFB2);
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r8a7791_register_scif(SCIFA2);
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r8a7791_register_scif(SCIF0);
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r8a7791_register_scif(SCIF1);
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r8a7791_register_scif(SCIF2);
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r8a7791_register_scif(SCIF3);
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r8a7791_register_scif(SCIF4);
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r8a7791_register_scif(SCIF5);
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r8a7791_register_scif(SCIFA3);
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r8a7791_register_scif(SCIFA4);
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r8a7791_register_scif(SCIFA5);
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r8a7791_register_cmt(00);
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}
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void __init r8a7791_add_standard_devices(void)
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{
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r8a7791_add_dt_devices();
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r8a7791_register_irqc(0);
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}
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void __init r8a7791_init_early(void)
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{
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#ifndef CONFIG_ARM_ARCH_TIMER
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shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
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#endif
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}
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#ifdef CONFIG_USE_OF
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static const char *r8a7791_boards_compat_dt[] __initdata = {
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"renesas,r8a7791",
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NULL,
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};
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DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
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.smp = smp_ops(r8a7791_smp_ops),
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.init_early = r8a7791_init_early,
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.init_time = rcar_gen2_timer_init,
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.dt_compat = r8a7791_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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