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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
214 lines
4.9 KiB
ArmAsm
214 lines
4.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
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*
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* Written by : Luke Lee
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* Copyright (C) 2005 Faraday Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the fa526.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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#define CACHE_DLINESIZE 16
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.text
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/*
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* cpu_fa526_proc_init()
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*/
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ENTRY(cpu_fa526_proc_init)
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ret lr
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/*
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* cpu_fa526_proc_fin()
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*/
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ENTRY(cpu_fa526_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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nop
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nop
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ret lr
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/*
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* cpu_fa526_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 4
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_fa526_reset)
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/* TODO: Use CP8 if possible... */
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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bic ip, ip, #0x0800 @ BTB off
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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nop
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nop
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ret r0
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ENDPROC(cpu_fa526_reset)
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.popsection
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/*
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* cpu_fa526_do_idle()
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*/
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.align 4
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ENTRY(cpu_fa526_do_idle)
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ret lr
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ENTRY(cpu_fa526_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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ret lr
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/* =============================== PageTable ============================== */
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/*
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* cpu_fa526_switch_mm(pgd)
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*
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* Set the translation base pointer to be as described by pgd.
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*
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* pgd: new page tables
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*/
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.align 4
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ENTRY(cpu_fa526_switch_mm)
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#ifdef CONFIG_MMU
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mov ip, #0
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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#else
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mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
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#endif
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
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#endif
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ret lr
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/*
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* cpu_fa526_set_pte_ext(ptep, pte, ext)
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*
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* Set a PTE and flush it out
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*/
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.align 4
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ENTRY(cpu_fa526_set_pte_ext)
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#ifdef CONFIG_MMU
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armv3_set_pte_ext
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mov r0, r0
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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ret lr
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.type __fa526_setup, #function
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__fa526_setup:
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/* On return of this routine, r0 must carry correct flags for CFG register */
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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#endif
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mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
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mov r0, #1
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mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client
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mcr p15, 0, r0, c3, c0 @ load domain access register
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mrc p15, 0, r0, c1, c0 @ get control register v4
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ldr r5, fa526_cr1_clear
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bic r0, r0, r5
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ldr r5, fa526_cr1_set
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orr r0, r0, r5
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ret lr
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.size __fa526_setup, . - __fa526_setup
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/*
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* .RVI ZFRS BLDP WCAM
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* ..11 1001 .111 1101
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*
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*/
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.type fa526_cr1_clear, #object
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.type fa526_cr1_set, #object
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fa526_cr1_clear:
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.word 0x3f3f
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fa526_cr1_set:
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.word 0x397D
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
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define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
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.section ".rodata"
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string cpu_arch_name, "armv4"
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string cpu_elf_name, "v4"
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string cpu_fa526_name, "FA526"
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.align
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.section ".proc.info.init", #alloc
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.type __fa526_proc_info,#object
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__fa526_proc_info:
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.long 0x66015261
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.long 0xff01fff1
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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initfn __fa526_setup, __fa526_proc_info
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF
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.long cpu_fa526_name
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.long fa526_processor_functions
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.long fa_tlb_fns
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.long fa_user_fns
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.long fa_cache_fns
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.size __fa526_proc_info, . - __fa526_proc_info
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