Stephen Boyd 5bc7532497 clk: tegra: Changes for v4.7-rc1 ... This set of changes contains a bunch of cleanups and minor fixes along with some new clocks, mainly on Tegra210, in preparation for supporting DisplayPort and HDMI 2.0. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJXI3fsAAoJEN0jrNd/PrOho7sP/3W87IOP5Ga+0CAuiBfl3oyx 99nJMzloiHSSe9aH1w9CZJEXr47iCmfN7yoXp0xCx0CAT/6lTlnzIE9cpblvxJLY GXwxpIHDFWndmwvnBTaw5YN8C/DjfgE8KPIYArE9yvP0X1lnU0IdbcMXT5Gu31ny 9Sh9csgZNcKJyTJ4VgzVJkpHWjE5/ngcud0JfuUiQNc3VsJInGroYxdE16WeYDPq zP+5LXPEZAJu/GJPFBtySnhaBcr6Nk/HQ4X1M8/fC5ocA4TfxWZTHqXg6RyHIgJM flM69aeh0uBlK5TEX99W7OiOTpXog8HSukrjMw53lJT69uitxRkt4RLm5PStp4Gr fMClyJzujF2FTO3+TXvLnyj0MwrFvmQHboFqDJUBFJ4XFwZAZH43v9dXVFlGltib qThUiSyzljjeco6XPRLTkHNjntA3rwixCb4Lq2J8MHgf7O2DSQuCBtuBswVXKyQQ JfQAOTPNzzCXA7NWJ34pbNaM6Ex0pPJFGQs+5Mpzo5XAXc9od/79+4ht4tJSZ+hb Su5oRlv0+EU44MddKOBX5FPBbBnI6lBl8fADiM+ld9oDdlHHgkqMxlradhjIWY0Q 9uz+qjUu6VrmvkCxNe6s0yepwHYoeBpbrmRIj2ZiokXcH4kyltpL8XpOvuWhm4pP tYmTNJJmCb/hd6MZhiKv =HcjN -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next Pull tegra clk driver changes from Thierry Reding: This set of changes contains a bunch of cleanups and minor fixes along with some new clocks, mainly on Tegra210, in preparation for supporting DisplayPort and HDMI 2.0. * tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: dfll: Reformat CVB frequency table clk: tegra: dfll: Properly clean up on failure and removal clk: tegra: dfll: Make code more comprehensible clk: tegra: dfll: Reference CVB table instead of copying data clk: tegra: dfll: Update kerneldoc clk: tegra: Fix PLL_U post divider and initial rate on Tegra30 clk: tegra: Initialize PLL_C to sane rate on Tegra30 clk: tegra: Fix pllre Tegra210 and add pll_re_out1 clk: tegra: Add sor_safe clock clk: tegra: dpaux and dpaux1 are fixed factor clocks clk: tegra: Add dpaux1 clock clk: tegra: Use correct parent for dpaux clock clk: tegra: Add fixed factor peripheral clock type clk: tegra: Special-case mipi-cal parent on Tegra114 clk: tegra: Remove trailing blank line clk: tegra: Constify peripheral clock registers clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs		2016-05-02 16:53:02 -07:00
..
at91_pmc.h	clk: at91: pmc: drop at91_pmc_base	2016-02-17 17:53:03 +01:00
bcm2835.h
clk-conf.h	clk: Add missing header for 'bool' definition to clk-conf.h	2015-08-25 10:54:06 -07:00
mmp.h	clk: mmp: stop using platform headers	2015-12-01 21:44:22 +01:00
mxs.h	ARM: mxs: remove custom .init_time hook	2013-09-29 21:09:34 +02:00
renesas.h	clk: renesas: cpg-mssr: Export cpg_mssr_{at,de}tach_dev()	2016-04-20 09:17:07 +02:00
tegra.h	clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs	2016-04-28 12:41:44 +02:00
ti.h	clk: ti: dpll: add support for specifying max rate for DPLLs	2016-04-15 17:26:18 -07:00
zynq.h	ARM: zynq: Map I/O memory on clkc init	2014-02-10 11:21:13 +01:00