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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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14ac00e033
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
327 lines
6.7 KiB
C
327 lines
6.7 KiB
C
/*
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* SuperH HSPI bus driver
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*
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* Copyright (C) 2011 Kuninori Morimoto
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*
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* Based on spi-sh.c:
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* Based on pxa2xx_spi.c:
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/timer.h>
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#include <linux/delay.h>
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#include <linux/list.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/sh_hspi.h>
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#define SPCR 0x00
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#define SPSR 0x04
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#define SPSCR 0x08
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#define SPTBR 0x0C
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#define SPRBR 0x10
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#define SPCR2 0x14
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/* SPSR */
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#define RXFL (1 << 2)
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struct hspi_priv {
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void __iomem *addr;
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struct spi_master *master;
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struct device *dev;
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struct clk *clk;
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};
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/*
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* basic function
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*/
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static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
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{
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iowrite32(val, hspi->addr + reg);
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}
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static u32 hspi_read(struct hspi_priv *hspi, int reg)
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{
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return ioread32(hspi->addr + reg);
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}
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static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
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{
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u32 val = hspi_read(hspi, reg);
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val &= ~mask;
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val |= set & mask;
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hspi_write(hspi, reg, val);
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}
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/*
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* transfer function
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*/
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static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
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{
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int t = 256;
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while (t--) {
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if ((mask & hspi_read(hspi, SPSR)) == val)
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return 0;
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udelay(10);
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}
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dev_err(hspi->dev, "timeout\n");
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return -ETIMEDOUT;
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}
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/*
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* spi master function
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*/
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#define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
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#define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1)
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static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
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{
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hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
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}
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static void hspi_hw_setup(struct hspi_priv *hspi,
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struct spi_message *msg,
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struct spi_transfer *t)
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{
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struct spi_device *spi = msg->spi;
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struct device *dev = hspi->dev;
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u32 spcr, idiv_clk;
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u32 rate, best_rate, min, tmp;
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/*
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* find best IDIV/CLKCx settings
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*/
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min = ~0;
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best_rate = 0;
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spcr = 0;
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for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
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rate = clk_get_rate(hspi->clk);
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/* IDIV calculation */
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if (idiv_clk & (1 << 5))
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rate /= 128;
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else
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rate /= 16;
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/* CLKCx calculation */
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rate /= (((idiv_clk & 0x1F) + 1) * 2);
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/* save best settings */
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tmp = abs(t->speed_hz - rate);
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if (tmp < min) {
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min = tmp;
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spcr = idiv_clk;
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best_rate = rate;
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}
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}
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if (spi->mode & SPI_CPHA)
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spcr |= 1 << 7;
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if (spi->mode & SPI_CPOL)
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spcr |= 1 << 6;
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dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate);
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hspi_write(hspi, SPCR, spcr);
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hspi_write(hspi, SPSR, 0x0);
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hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */
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}
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static int hspi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct hspi_priv *hspi = spi_master_get_devdata(master);
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struct spi_transfer *t;
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u32 tx;
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u32 rx;
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int ret, i;
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unsigned int cs_change;
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const int nsecs = 50;
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dev_dbg(hspi->dev, "%s\n", __func__);
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cs_change = 1;
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ret = 0;
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list_for_each_entry(t, &msg->transfers, transfer_list) {
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if (cs_change) {
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hspi_hw_setup(hspi, msg, t);
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hspi_hw_cs_enable(hspi);
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ndelay(nsecs);
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}
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cs_change = t->cs_change;
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for (i = 0; i < t->len; i++) {
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/* wait remains */
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ret = hspi_status_check_timeout(hspi, 0x1, 0);
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if (ret < 0)
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break;
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tx = 0;
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if (t->tx_buf)
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tx = (u32)((u8 *)t->tx_buf)[i];
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hspi_write(hspi, SPTBR, tx);
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/* wait receive */
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ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
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if (ret < 0)
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break;
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rx = hspi_read(hspi, SPRBR);
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if (t->rx_buf)
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((u8 *)t->rx_buf)[i] = (u8)rx;
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}
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msg->actual_length += t->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (cs_change) {
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ndelay(nsecs);
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hspi_hw_cs_disable(hspi);
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ndelay(nsecs);
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}
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}
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msg->status = ret;
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if (!cs_change) {
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ndelay(nsecs);
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hspi_hw_cs_disable(hspi);
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}
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spi_finalize_current_message(master);
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return ret;
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}
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static int hspi_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct spi_master *master;
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struct hspi_priv *hspi;
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struct clk *clk;
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int ret;
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/* get base addr */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "invalid resource\n");
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return -EINVAL;
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}
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master = spi_alloc_master(&pdev->dev, sizeof(*hspi));
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if (!master) {
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dev_err(&pdev->dev, "spi_alloc_master error.\n");
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return -ENOMEM;
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}
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clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "couldn't get clock\n");
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ret = -EINVAL;
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goto error0;
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}
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hspi = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, hspi);
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/* init hspi */
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hspi->master = master;
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hspi->dev = &pdev->dev;
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hspi->clk = clk;
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hspi->addr = devm_ioremap(hspi->dev,
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res->start, resource_size(res));
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if (!hspi->addr) {
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dev_err(&pdev->dev, "ioremap error.\n");
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ret = -ENOMEM;
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goto error1;
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}
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pm_runtime_enable(&pdev->dev);
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master->bus_num = pdev->id;
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master->mode_bits = SPI_CPOL | SPI_CPHA;
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master->dev.of_node = pdev->dev.of_node;
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master->auto_runtime_pm = true;
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master->transfer_one_message = hspi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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ret = devm_spi_register_master(&pdev->dev, master);
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if (ret < 0) {
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dev_err(&pdev->dev, "spi_register_master error.\n");
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goto error2;
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}
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return 0;
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error2:
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pm_runtime_disable(&pdev->dev);
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error1:
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clk_put(clk);
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error0:
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spi_master_put(master);
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return ret;
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}
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static int hspi_remove(struct platform_device *pdev)
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{
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struct hspi_priv *hspi = platform_get_drvdata(pdev);
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pm_runtime_disable(&pdev->dev);
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clk_put(hspi->clk);
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return 0;
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}
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static const struct of_device_id hspi_of_match[] = {
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{ .compatible = "renesas,hspi", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, hspi_of_match);
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static struct platform_driver hspi_driver = {
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.probe = hspi_probe,
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.remove = hspi_remove,
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.driver = {
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.name = "sh-hspi",
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.of_match_table = hspi_of_match,
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},
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};
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module_platform_driver(hspi_driver);
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MODULE_DESCRIPTION("SuperH HSPI bus driver");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
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MODULE_ALIAS("platform:sh-hspi");
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