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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 22:17:10 +07:00
e2d7933308
EPROBE_DEFER is not an error, hence printing an error message like clk: couldn't get clock 0 for /soc/display@feb00000 may confuse the user. Suppress error messages in case of probe deferral to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
148 lines
3.9 KiB
C
148 lines
3.9 KiB
C
/*
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* Copyright (C) 2014 Samsung Electronics Co., Ltd.
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* Sylwester Nawrocki <s.nawrocki@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/clk-conf.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/printk.h>
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static int __set_clk_parents(struct device_node *node, bool clk_supplier)
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{
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struct of_phandle_args clkspec;
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int index, rc, num_parents;
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struct clk *clk, *pclk;
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num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells");
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if (num_parents == -EINVAL)
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pr_err("clk: invalid value of clock-parents property at %s\n",
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node->full_name);
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for (index = 0; index < num_parents; index++) {
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rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
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"#clock-cells", index, &clkspec);
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if (rc < 0) {
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/* skip empty (null) phandles */
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if (rc == -ENOENT)
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continue;
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else
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return rc;
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}
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if (clkspec.np == node && !clk_supplier)
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return 0;
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pclk = of_clk_get_from_provider(&clkspec);
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if (IS_ERR(pclk)) {
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if (PTR_ERR(pclk) != -EPROBE_DEFER)
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pr_warn("clk: couldn't get parent clock %d for %s\n",
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index, node->full_name);
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return PTR_ERR(pclk);
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}
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rc = of_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", index, &clkspec);
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if (rc < 0)
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goto err;
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if (clkspec.np == node && !clk_supplier) {
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rc = 0;
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goto err;
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}
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clk = of_clk_get_from_provider(&clkspec);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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pr_warn("clk: couldn't get assigned clock %d for %s\n",
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index, node->full_name);
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rc = PTR_ERR(clk);
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goto err;
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}
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rc = clk_set_parent(clk, pclk);
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if (rc < 0)
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pr_err("clk: failed to reparent %s to %s: %d\n",
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__clk_get_name(clk), __clk_get_name(pclk), rc);
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clk_put(clk);
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clk_put(pclk);
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}
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return 0;
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err:
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clk_put(pclk);
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return rc;
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}
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static int __set_clk_rates(struct device_node *node, bool clk_supplier)
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{
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struct of_phandle_args clkspec;
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struct property *prop;
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const __be32 *cur;
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int rc, index = 0;
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struct clk *clk;
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u32 rate;
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of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
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if (rate) {
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rc = of_parse_phandle_with_args(node, "assigned-clocks",
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"#clock-cells", index, &clkspec);
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if (rc < 0) {
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/* skip empty (null) phandles */
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if (rc == -ENOENT)
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continue;
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else
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return rc;
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}
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if (clkspec.np == node && !clk_supplier)
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return 0;
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clk = of_clk_get_from_provider(&clkspec);
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if (IS_ERR(clk)) {
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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pr_warn("clk: couldn't get clock %d for %s\n",
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index, node->full_name);
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return PTR_ERR(clk);
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}
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rc = clk_set_rate(clk, rate);
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if (rc < 0)
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pr_err("clk: couldn't set %s clk rate to %d (%d), current rate: %ld\n",
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__clk_get_name(clk), rate, rc,
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clk_get_rate(clk));
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clk_put(clk);
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}
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index++;
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}
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return 0;
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}
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/**
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* of_clk_set_defaults() - parse and set assigned clocks configuration
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* @node: device node to apply clock settings for
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* @clk_supplier: true if clocks supplied by @node should also be considered
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*
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* This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
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* and sets any specified clock parents and rates. The @clk_supplier argument
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* should be set to true if @node may be also a clock supplier of any clock
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* listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
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* If @clk_supplier is false the function exits returning 0 as soon as it
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* determines the @node is also a supplier of any of the clocks.
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*/
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int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
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{
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int rc;
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if (!node)
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return 0;
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rc = __set_clk_parents(node, clk_supplier);
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if (rc < 0)
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return rc;
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return __set_clk_rates(node, clk_supplier);
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}
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EXPORT_SYMBOL_GPL(of_clk_set_defaults);
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