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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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127a770949
The granularity message has an extra "d":
pci 0000:02:00.0: PTM enabled, 4dns granularity
Remove the "d" so the message is simply "PTM enabled, 4ns granularity".
Fixes: 8b2ec318ee ("PCI: Add PTM clock granularity information")
Link: https://lore.kernel.org/r/20191106222420.10216-2-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Cc: Jonathan Yong <jonathan.yong@intel.com>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI Express Precision Time Measurement
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* Copyright (c) 2016, Intel Corporation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include "../pci.h"
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static void pci_ptm_info(struct pci_dev *dev)
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{
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char clock_desc[8];
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switch (dev->ptm_granularity) {
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case 0:
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snprintf(clock_desc, sizeof(clock_desc), "unknown");
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break;
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case 255:
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snprintf(clock_desc, sizeof(clock_desc), ">254ns");
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break;
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default:
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snprintf(clock_desc, sizeof(clock_desc), "%uns",
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dev->ptm_granularity);
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break;
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}
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pci_info(dev, "PTM enabled%s, %s granularity\n",
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dev->ptm_root ? " (root)" : "", clock_desc);
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}
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void pci_ptm_init(struct pci_dev *dev)
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{
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int pos;
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u32 cap, ctrl;
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u8 local_clock;
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struct pci_dev *ups;
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if (!pci_is_pcie(dev))
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return;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
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if (!pos)
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return;
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/*
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* Enable PTM only on interior devices (root ports, switch ports,
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* etc.) on the assumption that it causes no link traffic until an
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* endpoint enables it.
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*/
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if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
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pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
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return;
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pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
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local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
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/*
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* There's no point in enabling PTM unless it's enabled in the
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* upstream device or this device can be a PTM Root itself. Per
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* the spec recommendation (PCIe r3.1, sec 7.32.3), select the
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* furthest upstream Time Source as the PTM Root.
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*/
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ups = pci_upstream_bridge(dev);
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if (ups && ups->ptm_enabled) {
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ctrl = PCI_PTM_CTRL_ENABLE;
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if (ups->ptm_granularity == 0)
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dev->ptm_granularity = 0;
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else if (ups->ptm_granularity > local_clock)
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dev->ptm_granularity = ups->ptm_granularity;
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} else {
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if (cap & PCI_PTM_CAP_ROOT) {
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ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
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dev->ptm_root = 1;
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dev->ptm_granularity = local_clock;
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} else
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return;
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}
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ctrl |= dev->ptm_granularity << 8;
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pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
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dev->ptm_enabled = 1;
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pci_ptm_info(dev);
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}
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int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
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{
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int pos;
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u32 cap, ctrl;
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struct pci_dev *ups;
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if (!pci_is_pcie(dev))
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return -EINVAL;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
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if (!pos)
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return -EINVAL;
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pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
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if (!(cap & PCI_PTM_CAP_REQ))
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return -EINVAL;
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/*
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* For a PCIe Endpoint, PTM is only useful if the endpoint can
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* issue PTM requests to upstream devices that have PTM enabled.
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*
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* For Root Complex Integrated Endpoints, there is no upstream
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* device, so there must be some implementation-specific way to
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* associate the endpoint with a time source.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
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ups = pci_upstream_bridge(dev);
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if (!ups || !ups->ptm_enabled)
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return -EINVAL;
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dev->ptm_granularity = ups->ptm_granularity;
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} else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
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dev->ptm_granularity = 0;
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} else
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return -EINVAL;
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ctrl = PCI_PTM_CTRL_ENABLE;
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ctrl |= dev->ptm_granularity << 8;
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pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
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dev->ptm_enabled = 1;
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pci_ptm_info(dev);
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if (granularity)
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*granularity = dev->ptm_granularity;
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return 0;
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}
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EXPORT_SYMBOL(pci_enable_ptm);
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