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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1f50ddb4f4
The AMD64_LS_CFG MSR is a per core MSR on Family 17H CPUs. That means when hyperthreading is enabled the SSBD bit toggle needs to take both cores into account. Otherwise the following situation can happen: CPU0 CPU1 disable SSB disable SSB enable SSB <- Enables it for the Core, i.e. for CPU0 as well So after the SSB enable on CPU1 the task on CPU0 runs with SSB enabled again. On Intel the SSBD control is per core as well, but the synchronization logic is implemented behind the per thread SPEC_CTRL MSR. It works like this: CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL i.e. if one of the threads enables a mitigation then this affects both and the mitigation is only disabled in the core when both threads disabled it. Add the necessary synchronization logic for AMD family 17H. Unfortunately that requires a spinlock to serialize the access to the MSR, but the locks are only shared between siblings. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov <bp@suse.de> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
45 lines
1.2 KiB
C
45 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_SPECCTRL_H_
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#define _ASM_X86_SPECCTRL_H_
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#include <linux/thread_info.h>
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#include <asm/nospec-branch.h>
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/*
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* On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
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* the guest has, while on VMEXIT we restore the host view. This
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* would be easier if SPEC_CTRL were architecturally maskable or
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* shadowable for guests but this is not (currently) the case.
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* Takes the guest view of SPEC_CTRL MSR as a parameter.
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*/
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extern void x86_spec_ctrl_set_guest(u64);
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extern void x86_spec_ctrl_restore_host(u64);
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/* AMD specific Speculative Store Bypass MSR data */
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extern u64 x86_amd_ls_cfg_base;
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extern u64 x86_amd_ls_cfg_ssbd_mask;
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/* The Intel SPEC CTRL MSR base value cache */
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extern u64 x86_spec_ctrl_base;
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static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
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{
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BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
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return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
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}
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static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
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{
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return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
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}
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#ifdef CONFIG_SMP
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extern void speculative_store_bypass_ht_init(void);
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#else
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static inline void speculative_store_bypass_ht_init(void) { }
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#endif
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extern void speculative_store_bypass_update(void);
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#endif
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