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2b468ef0e7
According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte addressing mode should be entered as follows: <quote> To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. </quote> Micron's portable way to perform this for all types of Micron flash is to first issue a write enable, then switch the addressing mode followed by a write disable to avoid leaving the flash in a write- able state. Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com> [Brian: reworked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> |
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.. | ||
chips | ||
devices | ||
lpddr | ||
maps | ||
nand | ||
onenand | ||
tests | ||
ubi | ||
afs.c | ||
ar7part.c | ||
bcm47xxpart.c | ||
bcm63xxpart.c | ||
cmdlinepart.c | ||
ftl.c | ||
inftlcore.c | ||
inftlmount.c | ||
Kconfig | ||
Makefile | ||
mtd_blkdevs.c | ||
mtdblock_ro.c | ||
mtdblock.c | ||
mtdchar.c | ||
mtdconcat.c | ||
mtdcore.c | ||
mtdcore.h | ||
mtdoops.c | ||
mtdpart.c | ||
mtdsuper.c | ||
mtdswap.c | ||
nftlcore.c | ||
nftlmount.c | ||
ofpart.c | ||
redboot.c | ||
rfd_ftl.c | ||
sm_ftl.c | ||
sm_ftl.h | ||
ssfdc.c |