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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8784692d28
This enables the Broadcom uart bluetooth driver on uart0 and gives it ownership of its gpios. In order to use this, you must enable the following kconfig options: - CONFIG_BT_HCIUART_BCM - CONFIG_SERIAL_DEV This is applicable to rk3288-veyron series boards that use the bcm43540 wifi+bt chips. As part of this change, also refactor the pinctrl across the various boards. All the boards using broadcom bluetooth shouldn't touch the bt_dev_wake pin. Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20191127223909.253873-2-abhishekpandit@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
325 lines
5.0 KiB
Plaintext
325 lines
5.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Veyron Speedy Rev 1+ board device tree source
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*
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* Copyright 2015 Google, Inc
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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#include "rk3288-veyron-broadcom-bluetooth.dtsi"
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#include "cros-ec-sbs.dtsi"
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/ {
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model = "Google Speedy";
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compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
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"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
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"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
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"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
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"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
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};
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&cpu_alert0 {
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temperature = <65000>;
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};
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&cpu_alert1 {
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temperature = <70000>;
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};
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&cpu_crit {
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temperature = <90000>;
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};
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&edp {
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/delete-property/pinctrl-names;
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/delete-property/pinctrl-0;
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force-hpd;
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};
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&gpu_alert0 {
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temperature = <80000>;
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};
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&gpu_crit {
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temperature = <90000>;
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l>;
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};
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&sdmmc {
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disable-wp;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
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&sdmmc_bus4>;
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};
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&vcc_5v {
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enable-active-high;
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gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&drv_5v>;
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc50_hdmi_en>;
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};
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&gpio0 {
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gpio-line-names = "PMIC_SLEEP_AP",
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"DDRIO_PWROFF",
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"DDRIO_RETEN",
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"TS3A227E_INT_L",
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"PMIC_INT_L",
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"PWR_KEY_L",
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"AP_LID_INT_L",
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"EC_IN_RW",
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"AC_PRESENT_AP",
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/*
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* RECOVERY_SW_L is Chrome OS ABI. Schematics call
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* it REC_MODE_L.
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*/
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"RECOVERY_SW_L",
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"OTP_OUT",
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"HOST1_PWR_EN",
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"USBOTG_PWREN_H",
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"AP_WARM_RESET_H",
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"nFALUT2",
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"I2C0_SDA_PMIC",
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"I2C0_SCL_PMIC",
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"SUSPEND_L",
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"USB_INT";
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};
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&gpio2 {
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gpio-line-names = "CONFIG0",
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"CONFIG1",
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"CONFIG2",
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"",
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"",
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"",
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"",
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"CONFIG3",
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"PWRLIMIT#_CPU",
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"EMMC_RST_L",
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"",
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"",
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"BL_PWR_EN",
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"AVDD_1V8_DISP_EN";
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};
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&gpio3 {
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gpio-line-names = "FLASH0_D0",
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"FLASH0_D1",
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"FLASH0_D2",
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"FLASH0_D3",
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"FLASH0_D4",
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"FLASH0_D5",
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"FLASH0_D6",
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"FLASH0_D7",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"FLASH0_CS2/EMMC_CMD",
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"",
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"FLASH0_DQS/EMMC_CLKO";
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};
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&gpio4 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"UART0_RXD",
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"UART0_TXD",
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"UART0_CTS",
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"UART0_RTS",
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"SDIO0_D0",
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"SDIO0_D1",
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"SDIO0_D2",
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"SDIO0_D3",
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"SDIO0_CMD",
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"SDIO0_CLK",
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"BT_DEV_WAKE",
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"",
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"WIFI_ENABLE_H",
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"BT_ENABLE_L",
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"WIFI_HOST_WAKE",
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"BT_HOST_WAKE";
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};
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&gpio5 {
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gpio-line-names = "",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"SPI0_CLK",
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"SPI0_CS0",
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"SPI0_TXD",
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"SPI0_RXD",
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"",
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"",
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"",
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"VCC50_HDMI_EN";
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};
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&gpio6 {
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gpio-line-names = "I2S0_SCLK",
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"I2S0_LRCK_RX",
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"I2S0_LRCK_TX",
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"I2S0_SDI",
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"I2S0_SDO0",
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"HP_DET_H",
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"ALS_INT", /* not connected */
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"INT_CODEC",
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"I2S0_CLK",
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"I2C2_SDA",
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"I2C2_SCL",
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"MICDET",
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"",
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"",
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"",
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"",
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"SDMMC_D0",
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"SDMMC_D1",
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"SDMMC_D2",
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"SDMMC_D3",
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"SDMMC_CLK",
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"SDMMC_CMD";
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};
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&gpio7 {
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gpio-line-names = "LCDC_BL",
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"PWM_LOG",
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"BL_EN",
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"TRACKPAD_INT",
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"TPM_INT_H",
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"SDMMC_DET_L",
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/*
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* AP_FLASH_WP_L is Chrome OS ABI. Schematics call
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* it FW_WP_AP.
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*/
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"AP_FLASH_WP_L",
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"EC_INT",
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"CPU_NMI",
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"DVS_OK",
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"",
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"EDP_HOTPLUG",
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"DVS1",
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"nFALUT1",
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"LCD_EN",
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"DVS2",
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"VCC5V_GOOD_H",
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"I2C4_SDA_TP",
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"I2C4_SCL_TP",
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"I2C5_SDA_HDMI",
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"I2C5_SCL_HDMI",
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"5V_DRV",
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"UART2_RXD",
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"UART2_TXD";
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};
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&gpio8 {
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gpio-line-names = "RAM_ID0",
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"RAM_ID1",
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"RAM_ID2",
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"RAM_ID3",
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"I2C1_SDA_TPM",
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"I2C1_SCL_TPM",
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"SPI2_CLK",
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"SPI2_CS0",
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"SPI2_RXD",
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"SPI2_TXD";
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};
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&pinctrl {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <
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/* Common for sleep and wake, but no owners */
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&ddr0_retention
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&ddrio_pwroff
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&global_pwroff
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/* Wake only */
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&suspend_l_wake
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>;
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pinctrl-1 = <
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/* Common for sleep and wake, but no owners */
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&ddr0_retention
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&ddrio_pwroff
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&global_pwroff
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/* Sleep only */
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&suspend_l_sleep
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>;
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buck-5v {
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drv_5v: drv-5v {
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rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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hdmi {
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vcc50_hdmi_en: vcc50-hdmi-en {
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rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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