mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 23:48:53 +07:00
ba33ea811e
Pull x86 asm updates from Ingo Molnar:
"This is another big update. Main changes are:
- lots of x86 system call (and other traps/exceptions) entry code
enhancements. In particular the complex parts of the 64-bit entry
code have been migrated to C code as well, and a number of dusty
corners have been refreshed. (Andy Lutomirski)
- vDSO special mapping robustification and general cleanups (Andy
Lutomirski)
- cpufeature refactoring, cleanups and speedups (Borislav Petkov)
- lots of other changes ..."
* 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (64 commits)
x86/cpufeature: Enable new AVX-512 features
x86/entry/traps: Show unhandled signal for i386 in do_trap()
x86/entry: Call enter_from_user_mode() with IRQs off
x86/entry/32: Change INT80 to be an interrupt gate
x86/entry: Improve system call entry comments
x86/entry: Remove TIF_SINGLESTEP entry work
x86/entry/32: Add and check a stack canary for the SYSENTER stack
x86/entry/32: Simplify and fix up the SYSENTER stack #DB/NMI fixup
x86/entry: Only allocate space for tss_struct::SYSENTER_stack if needed
x86/entry: Vastly simplify SYSENTER TF (single-step) handling
x86/entry/traps: Clear DR6 early in do_debug() and improve the comment
x86/entry/traps: Clear TIF_BLOCKSTEP on all debug exceptions
x86/entry/32: Restore FLAGS on SYSEXIT
x86/entry/32: Filter NT and speed up AC filtering in SYSENTER
x86/entry/compat: In SYSENTER, sink AC clearing below the existing FLAGS test
selftests/x86: In syscall_nt, test NT|TF as well
x86/asm-offsets: Remove PARAVIRT_enabled
x86/entry/32: Introduce and use X86_BUG_ESPFIX instead of paravirt_enabled
uprobes: __create_xol_area() must nullify xol_mapping.fault
x86/cpufeature: Create a new synthetic cpu capability for machine check recovery
...
109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
#include <linux/kernel.h>
|
|
#include <linux/mm.h>
|
|
#include <asm/cpufeature.h>
|
|
#include <asm/msr.h>
|
|
#include "cpu.h"
|
|
|
|
static void early_init_transmeta(struct cpuinfo_x86 *c)
|
|
{
|
|
u32 xlvl;
|
|
|
|
/* Transmeta-defined flags: level 0x80860001 */
|
|
xlvl = cpuid_eax(0x80860000);
|
|
if ((xlvl & 0xffff0000) == 0x80860000) {
|
|
if (xlvl >= 0x80860001)
|
|
c->x86_capability[CPUID_8086_0001_EDX] = cpuid_edx(0x80860001);
|
|
}
|
|
}
|
|
|
|
static void init_transmeta(struct cpuinfo_x86 *c)
|
|
{
|
|
unsigned int cap_mask, uk, max, dummy;
|
|
unsigned int cms_rev1, cms_rev2;
|
|
unsigned int cpu_rev, cpu_freq = 0, cpu_flags, new_cpu_rev;
|
|
char cpu_info[65];
|
|
|
|
early_init_transmeta(c);
|
|
|
|
cpu_detect_cache_sizes(c);
|
|
|
|
/* Print CMS and CPU revision */
|
|
max = cpuid_eax(0x80860000);
|
|
cpu_rev = 0;
|
|
if (max >= 0x80860001) {
|
|
cpuid(0x80860001, &dummy, &cpu_rev, &cpu_freq, &cpu_flags);
|
|
if (cpu_rev != 0x02000000) {
|
|
pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n",
|
|
(cpu_rev >> 24) & 0xff,
|
|
(cpu_rev >> 16) & 0xff,
|
|
(cpu_rev >> 8) & 0xff,
|
|
cpu_rev & 0xff,
|
|
cpu_freq);
|
|
}
|
|
}
|
|
if (max >= 0x80860002) {
|
|
cpuid(0x80860002, &new_cpu_rev, &cms_rev1, &cms_rev2, &dummy);
|
|
if (cpu_rev == 0x02000000) {
|
|
pr_info("CPU: Processor revision %08X, %u MHz\n",
|
|
new_cpu_rev, cpu_freq);
|
|
}
|
|
pr_info("CPU: Code Morphing Software revision %u.%u.%u-%u-%u\n",
|
|
(cms_rev1 >> 24) & 0xff,
|
|
(cms_rev1 >> 16) & 0xff,
|
|
(cms_rev1 >> 8) & 0xff,
|
|
cms_rev1 & 0xff,
|
|
cms_rev2);
|
|
}
|
|
if (max >= 0x80860006) {
|
|
cpuid(0x80860003,
|
|
(void *)&cpu_info[0],
|
|
(void *)&cpu_info[4],
|
|
(void *)&cpu_info[8],
|
|
(void *)&cpu_info[12]);
|
|
cpuid(0x80860004,
|
|
(void *)&cpu_info[16],
|
|
(void *)&cpu_info[20],
|
|
(void *)&cpu_info[24],
|
|
(void *)&cpu_info[28]);
|
|
cpuid(0x80860005,
|
|
(void *)&cpu_info[32],
|
|
(void *)&cpu_info[36],
|
|
(void *)&cpu_info[40],
|
|
(void *)&cpu_info[44]);
|
|
cpuid(0x80860006,
|
|
(void *)&cpu_info[48],
|
|
(void *)&cpu_info[52],
|
|
(void *)&cpu_info[56],
|
|
(void *)&cpu_info[60]);
|
|
cpu_info[64] = '\0';
|
|
pr_info("CPU: %s\n", cpu_info);
|
|
}
|
|
|
|
/* Unhide possibly hidden capability flags */
|
|
rdmsr(0x80860004, cap_mask, uk);
|
|
wrmsr(0x80860004, ~0, uk);
|
|
c->x86_capability[CPUID_1_EDX] = cpuid_edx(0x00000001);
|
|
wrmsr(0x80860004, cap_mask, uk);
|
|
|
|
/* All Transmeta CPUs have a constant TSC */
|
|
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
|
|
|
|
#ifdef CONFIG_SYSCTL
|
|
/*
|
|
* randomize_va_space slows us down enormously;
|
|
* it probably triggers retranslation of x86->native bytecode
|
|
*/
|
|
randomize_va_space = 0;
|
|
#endif
|
|
}
|
|
|
|
static const struct cpu_dev transmeta_cpu_dev = {
|
|
.c_vendor = "Transmeta",
|
|
.c_ident = { "GenuineTMx86", "TransmetaCPU" },
|
|
.c_early_init = early_init_transmeta,
|
|
.c_init = init_transmeta,
|
|
.c_x86_vendor = X86_VENDOR_TRANSMETA,
|
|
};
|
|
|
|
cpu_dev_register(transmeta_cpu_dev);
|