mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1eb8c695bd
Use RFS infrastructure and flow steering in HW to keep CPU affinity of rx interrupts and application per TCP stream. A flow steering filter is added to the HW whenever the RFS ndo callback is invoked by core networking code. Because the invocation takes place in interrupt context, the actual setup of HW is done using workqueue. Whenever new filter is added, the driver checks for expiry of existing filters. Since there's window in time between the point where the core RFS code invoked the ndo callback, to the point where the HW is configured from the workqueue context, the 2nd, 3rd etc packets from that stream will cause the net core to invoke the callback again and again. To prevent inefficient/double configuration of the HW, the filters are kept in a database which is indexed using hash function to enable fast access. Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
181 lines
4.8 KiB
C
181 lines
4.8 KiB
C
/*
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* Copyright (c) 2007 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <linux/mlx4/cq.h>
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#include <linux/mlx4/qp.h>
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#include <linux/mlx4/cmd.h>
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#include "mlx4_en.h"
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static void mlx4_en_cq_event(struct mlx4_cq *cq, enum mlx4_event event)
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{
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return;
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}
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int mlx4_en_create_cq(struct mlx4_en_priv *priv,
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struct mlx4_en_cq *cq,
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int entries, int ring, enum cq_type mode)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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int err;
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cq->size = entries;
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cq->buf_size = cq->size * sizeof(struct mlx4_cqe);
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cq->ring = ring;
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cq->is_tx = mode;
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spin_lock_init(&cq->lock);
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err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres,
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cq->buf_size, 2 * PAGE_SIZE);
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if (err)
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return err;
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err = mlx4_en_map_buffer(&cq->wqres.buf);
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if (err)
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mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
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else
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cq->buf = (struct mlx4_cqe *) cq->wqres.buf.direct.buf;
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return err;
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}
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int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
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int cq_idx)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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int err = 0;
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char name[25];
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struct cpu_rmap *rmap =
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#ifdef CONFIG_RFS_ACCEL
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priv->dev->rx_cpu_rmap;
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#else
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NULL;
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#endif
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cq->dev = mdev->pndev[priv->port];
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cq->mcq.set_ci_db = cq->wqres.db.db;
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cq->mcq.arm_db = cq->wqres.db.db + 1;
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*cq->mcq.set_ci_db = 0;
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*cq->mcq.arm_db = 0;
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memset(cq->buf, 0, cq->buf_size);
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if (cq->is_tx == RX) {
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if (mdev->dev->caps.comp_pool) {
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if (!cq->vector) {
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sprintf(name, "%s-%d", priv->dev->name,
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cq->ring);
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/* Set IRQ for specific name (per ring) */
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if (mlx4_assign_eq(mdev->dev, name, rmap,
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&cq->vector)) {
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cq->vector = (cq->ring + 1 + priv->port)
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% mdev->dev->caps.num_comp_vectors;
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mlx4_warn(mdev, "Failed Assigning an EQ to "
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"%s ,Falling back to legacy EQ's\n",
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name);
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}
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}
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} else {
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cq->vector = (cq->ring + 1 + priv->port) %
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mdev->dev->caps.num_comp_vectors;
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}
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} else {
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/* For TX we use the same irq per
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ring we assigned for the RX */
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struct mlx4_en_cq *rx_cq;
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cq_idx = cq_idx % priv->rx_ring_num;
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rx_cq = &priv->rx_cq[cq_idx];
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cq->vector = rx_cq->vector;
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}
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if (!cq->is_tx)
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cq->size = priv->rx_ring[cq->ring].actual_size;
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err = mlx4_cq_alloc(mdev->dev, cq->size, &cq->wqres.mtt, &mdev->priv_uar,
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cq->wqres.db.dma, &cq->mcq, cq->vector, 0);
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if (err)
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return err;
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cq->mcq.comp = cq->is_tx ? mlx4_en_tx_irq : mlx4_en_rx_irq;
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cq->mcq.event = mlx4_en_cq_event;
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if (!cq->is_tx) {
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netif_napi_add(cq->dev, &cq->napi, mlx4_en_poll_rx_cq, 64);
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napi_enable(&cq->napi);
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}
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return 0;
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}
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void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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mlx4_en_unmap_buffer(&cq->wqres.buf);
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mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size);
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if (priv->mdev->dev->caps.comp_pool && cq->vector)
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mlx4_release_eq(priv->mdev->dev, cq->vector);
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cq->vector = 0;
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cq->buf_size = 0;
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cq->buf = NULL;
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}
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void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
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{
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if (!cq->is_tx) {
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napi_disable(&cq->napi);
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netif_napi_del(&cq->napi);
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}
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mlx4_cq_free(priv->mdev->dev, &cq->mcq);
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}
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/* Set rx cq moderation parameters */
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int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
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{
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return mlx4_cq_modify(priv->mdev->dev, &cq->mcq,
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cq->moder_cnt, cq->moder_time);
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}
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int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq)
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{
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mlx4_cq_arm(&cq->mcq, MLX4_CQ_DB_REQ_NOT, priv->mdev->uar_map,
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&priv->mdev->uar_lock);
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return 0;
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}
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